diff options
author | Marc Jones <marcj303@gmail.com> | 2017-05-15 18:55:11 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:46:18 +0000 |
commit | 1587dc8a2b4ddfe110cd0239c6506a320cccac96 (patch) | |
tree | ab9b3b3ae63461e9fa8caf4c3fe4410f78f664c3 /src/soc/amd/stoneyridge/chip.c | |
parent | 21cde8b83227fa324f246672b1e2d58408ea6bf8 (diff) |
soc/amd/stoneyridge: Add northbridge support
Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/chip.c')
-rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 33 |
1 files changed, 27 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 3faf536ef9..78a29f872d 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -12,25 +12,46 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include <chip.h> +#include <cpu/amd/mtrr.h> +#include <cpu/cpu.h> #include <device/device.h> #include <device/pci.h> #include <soc/hudson.h> +#include <soc/northbridge.h> -static void pci_domain_set_resources(device_t dev) +static void cpu_bus_init(device_t dev) { - assign_resources(dev->link_list); + initialize_cpus(dev->link_list); } -static struct device_operations pci_domain_ops = { - .set_resources = &pci_domain_set_resources, +struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = &cpu_bus_init, + .scan_bus = cpu_bus_scan, }; -static struct device_operations cpu_bus_ops = { +struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, }; static void enable_dev(device_t dev) { + static int done = 0; + + if (!done) { + setup_bsp_ramtop(); + done = 1; + } + /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; @@ -49,6 +70,7 @@ static void soc_init(void *chip_info) static void soc_final(void *chip_info) { hudson_final(chip_info); + fam15_finalize(chip_info); } struct chip_operations soc_amd_stoneyridge_ops = { @@ -57,4 +79,3 @@ struct chip_operations soc_amd_stoneyridge_ops = { .init = &soc_init, .final = &soc_final }; - |