coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-02-12	soc/amd/common: Remove redundant ACPI S3 test	Kyösti Mälkki
2019-01-23	soc/{amd,intel}: Remove needless '&' on function pointers	Elyes HAOUAS
2018-11-12	src: Remove unneeded include "{arch,cpu}/cpu.h"	Elyes HAOUAS
2018-10-31	soc/amd/stoneyridge: Get rid of domain_read_resources	Martin Roth
2018-07-27	soc/amd/stoneyridge: Add IGFX device ACPI ASL entry	Marc Jones
2018-06-01	soc/amd/stoneyridge: Add ACPI device name lookup	Marc Jones
2018-05-23	soc/amd/stoneyridge/: Get rid of device_t	Elyes HAOUAS
2018-05-18	soc/amd/stoneyridge: Support ACPI USB code generation	Duncan Laurie
2018-05-08	{mb,nb,soc}: Remove references to pci_bus_default_ops()	Nico Huber
2018-02-12	amd/stoneyridge: Add S3 support to POST	Marshall Dawson
2018-01-25	soc/amd/stoneyridge: Add I2C devicetree support.	Justin TerAvest
2018-01-25	src/amd/stoneyridge: Add devicetree ACPI names	Justin TerAvest
2017-12-22	soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init()	Richard Spiegel
2017-12-15	soc/amd/common: Update agesawrapper_call.h	Richard Spiegel
2017-12-12	soc/amd/common: Move Agesa related headers	Richard Spiegel
2017-11-14	soc/amd/stoneyridge: Load SMU fimware using PSP	Marshall Dawson
2017-11-04	soc/amd/stoneyridge: remove superfluous NULL field initialization	Aaron Durbin
2017-09-27	amd/stoneyridge: Move AmdInitEnv to ramstage	Marshall Dawson
2017-09-27	amd/stoneyridge: Convert MP init to mp_init_with_smm	Marshall Dawson
2017-08-14	stoneyridge: Fix CPU ASL \_PR table	Marc Jones
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-06-27	soc/amd/stoneyridge: Fix most checkpatch errors	Marshall Dawson
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones