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If there are multiple statements that are conditional on the same
Kconfig option, group them and move the condition check around the
statement. If there's only one statement depending on one condition, use
the short form instead.
Change-Id: I89cb17954150c146ffc762d8cb2e3b3b374924de
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47876
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix function call to invoke 16-bit read in 16-bit api instead of 8-bit read.
Signed-off-by: Igor Bagnucki <bagnucki02@gmail.com>
Change-Id: Ifd9079fc6446125e0e58402fdb64bc198bb8e381
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The Embedded Firmware Structure should contain SPI speed, mode
and Micron support for the PSP to program. Add Kconfig options
to specify these values to use for future platform changes.
BUG=b:158755102
TEST=Test menuconfig and platform build for Trembyle and Mandolin.
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42567
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BIT(x) needs <types.h>.
Change-Id: Icaeda969cae52d9c62d976db4ead0e734efa838c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:161366241
TEST=Build & boot Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ied7789e9315c75174df9a686c831c5a969ce3bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Because there was a lot of discussion about the size increase,
I also looked at the impact of calling the get_spi_bar() function
vs reading spi_base directly and just not worring about whether
or not spi_base was already set.
Using the spi_base variable directly is 77 bytes bytes for all 6
functions. it's roughly double the size to call the function at
153 bytes. This was almost entirely due to setting up a call stack.
If we add an assert into each function to make sure that the spi_base
variable is set, it doubles from the size of the function call to
333 bytes.
For my money, the function call is the best bet, because it not only
protects us from using spi_base before it's set, it also gets the
value for us (at least on x86, on the PSP, it still just dies.)
BUG=b:161366241
TEST: Build
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0b0d005426ef90f09bf090789acb9d6383f17bd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Previously, the spi base address code was using a number of different
functions in a way that didn't work for use on the PSP.
This patch consolidates all of that to a single saved value that gets
the LPC SPI base address by default on X86, and allows the PSP to set
it to a different value.
BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:41194 got rid of "this file is part of" lines. However, there are
some changes that landed right around the same time including those
lines. This change uses the following command to drop the lines from
new files:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic3c1d717416f6b7e946f84748e2b260552c06a1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41342
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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fch_spi_ctrl.c uses read*()/write*() functions which are declared in
arch/mmio.h. This change includes the file arch/mmio.h in
fch_spi_ctrl.c.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6540004512af1f59f5fb300a3a4818b87ad94bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change adds support for following SPI configuration functions to
common block SPI driver and exposes them to be used by SoC:
1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM,
enables prefetching, disables 4dw burst mode and sets SPI speed and mode.
2. fch_spi_config_modes(): This allows SoC to configure SPI speed and
mode. It uses SPI settings from soc_amd_common_config to configure the
speed and mode.
These functions expect SoC to include soc_amd_common_config in SoC
chip config and mainboard to configure these settings in device tree.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41248
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This removes all the duplicated code and logic and leverages
the existing ones in libraries themselves. The current side
effect is that protection cannot be fully enabled because the
read, write, and write enable command are not exposed in struct
spi_flash currently. That support can be revised if protection
scheme makes sense for our use-cases once it's better understood.
BUG=b:146928174
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8faf9cc719ee33dd9f03fb74b579b02bbc6a5e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37957
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When checking that command and data fit in the FIFO, don't count the first
byte. The command doesn't go through the FIFO.
TEST=confirm error (4+68>71) goes away on Mandolin
BUG=b:146225550
Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Use MIN() and MAX() defined in commonlib/helpers.h
Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37454
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the POSIX standard, %p is supposed to print a pointer "as
if by %#x", meaning the "0x" prefix should automatically be prepended.
All other implementations out there (glibc, Linux, even libpayload) do
this, so we should make coreboot match. This patch changes vtxprintf()
accordingly and removes any explicit instances of "0x%p" from existing
format strings.
How to handle zero padding is less clear: the official POSIX definition
above technically says there should be no automatic zero padding, but in
practice most other implementations seem to do it and I assume most
programmers would prefer it. The way chosen here is to always zero-pad
to 32 bits, even on a 64-bit system. The rationale for this is that even
on 64-bit systems, coreboot always avoids using any memory above 4GB for
itself, so in practice all pointers should fit in that range and padding
everything to 64 bits would just hurt readability. Padding it this way
also helps pointers that do exceed 4GB (e.g. prints from MMU config on
some arm64 systems) stand out better from the others.
Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
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Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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All solid state devices have vendor id defined by JEDEC specification JEP106,
which originally allocated only 7 bits for it plus parity. When number of
vendors exploded beyond 126, a banking proposition came maintaining
compatibility with older vendors while allowing for 4 extra bits (16 banks)
through the introduction of the concept "Continuation code", denoted by the
byte value of 0x7f.
Examples:
0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o
0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2
BUG=b:141535133
TEST=Build and boot grunt.
Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Create a new SPI code that overrides flash operations and uses the SPI
controller within the FCH to its fullest.
Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public)
BUG=b:136595978
TEST=Build and boot grunt using this code, with debug enabled. Check
output.
Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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