diff options
author | Julius Werner <jwerner@chromium.org> | 2019-12-09 13:03:29 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-11 11:38:59 +0000 |
commit | 540a98001d05a7b780e415c34d14a97b14e44ac6 (patch) | |
tree | db4cffc987097c64fb6c6be996e57bdcbf9786ac /src/soc/amd/common/block/spi | |
parent | 86da00db899c4c58df90b4270082007c871169c7 (diff) |
printf: Automatically prefix %p with 0x
According to the POSIX standard, %p is supposed to print a pointer "as
if by %#x", meaning the "0x" prefix should automatically be prepended.
All other implementations out there (glibc, Linux, even libpayload) do
this, so we should make coreboot match. This patch changes vtxprintf()
accordingly and removes any explicit instances of "0x%p" from existing
format strings.
How to handle zero padding is less clear: the official POSIX definition
above technically says there should be no automatic zero padding, but in
practice most other implementations seem to do it and I assume most
programmers would prefer it. The way chosen here is to always zero-pad
to 32 bits, even on a 64-bit system. The rationale for this is that even
on 64-bit systems, coreboot always avoids using any memory above 4GB for
itself, so in practice all pointers should fit in that range and padding
everything to 64 bits would just hurt readability. Padding it this way
also helps pointers that do exceed 4GB (e.g. prints from MMU config on
some arm64 systems) stand out better from the others.
Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Diffstat (limited to 'src/soc/amd/common/block/spi')
-rw-r--r-- | src/soc/amd/common/block/spi/fch_spi_flash.c | 2 | ||||
-rw-r--r-- | src/soc/amd/common/block/spi/fch_spi_special.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/spi/fch_spi_flash.c b/src/soc/amd/common/block/spi/fch_spi_flash.c index 40dd0e2996..72bc5d6ea5 100644 --- a/src/soc/amd/common/block/spi/fch_spi_flash.c +++ b/src/soc/amd/common/block/spi/fch_spi_flash.c @@ -200,7 +200,7 @@ static int fch_spi_flash_write(const struct spi_flash *flash, uint32_t offset, s cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; #if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) - printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu" + printk(BIOS_DEBUG, "PP: %p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu" "\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif diff --git a/src/soc/amd/common/block/spi/fch_spi_special.c b/src/soc/amd/common/block/spi/fch_spi_special.c index fa3c00ac84..27bea05143 100644 --- a/src/soc/amd/common/block/spi/fch_spi_special.c +++ b/src/soc/amd/common/block/spi/fch_spi_special.c @@ -56,7 +56,7 @@ int non_standard_sst_write_aai(u32 offset, size_t len, const void *buf, size_t s for (actual = start; actual < len - 1; actual += 2) { #if CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG) - printk(BIOS_DEBUG, "PP: 0x%p => cmd = { 0x%02x 0x%06lx }" + printk(BIOS_DEBUG, "PP: %p => cmd = { 0x%02x 0x%06lx }" " chunk_len = 2\n", buf + actual, cmd[0], (offset + actual)); #endif |