soc/amd/common: Move spi access functions into their own file

Because there was a lot of discussion about the size increase,
I also looked at the impact of calling the get_spi_bar() function
vs reading spi_base directly and just not worring about whether
or not spi_base was already set.

Using the spi_base variable directly is 77 bytes bytes for all 6
functions. it's roughly double the size to call the function at
153 bytes.  This was almost entirely due to setting up a call stack.
If we add an assert into each function to make sure that the spi_base
variable is set, it doubles from the size of the function call to
333 bytes.

For my money, the function call is the best bet, because it not only
protects us from using spi_base before it's set, it also gets the
value for us (at least on x86, on the PSP, it still just dies.)

BUG=b:161366241
TEST: Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0b0d005426ef90f09bf090789acb9d6383f17bd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

4 files changed, 61 insertions, 39 deletions

diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc
index 3d541b7052..c8b733fe04 100644
--- a/src/soc/amd/common/block/spi/Makefile.inc
+++ b/src/soc/amd/common/block/spi/Makefile.inc
@@ -18,4 +18,11 @@ ifeq ($(CONFIG_SPI_FLASH_SMM),y)
 smm-y += fch_spi.c
 endif
 
-endif
+bootblock-y += fch_spi_util.c
+romstage-y += fch_spi_util.c
+postcar-y += fch_spi_util.c
+ramstage-y += fch_spi_util.c
+verstage-y += fch_spi_util.c
+smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_util.c
+
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_SPI
diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
index bac1452709..175be794ad 100644
--- a/src/soc/amd/common/block/spi/fch_spi.c
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -4,27 +4,10 @@
 #include <amdblocks/lpc.h>
 #include <amdblocks/spi.h>
 #include <arch/mmio.h>
-#include <assert.h>
 #include <console/console.h>
 #include <soc/iomap.h>
 #include <stdint.h>
 
-static uintptr_t spi_base;
-
-void spi_set_base(void *base)
-{
-	spi_base = (uintptr_t)base;
-}
-
-uintptr_t spi_get_bar(void)
-{
-	if (ENV_X86 && !spi_base)
-		spi_set_base((void *)lpc_get_spibase());
-	ASSERT(spi_base);
-
-	return spi_base;
-}
-
 static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)
 {
 	uintptr_t base = spi_get_bar();
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index 0be6b0e72f..1e0c31ab27 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/mmio.h>
 #include <console/console.h>
 #include <spi_flash.h>
 #include <soc/pci_devs.h>
@@ -30,26 +29,6 @@
 #define   SPI_FIFO_RD_PTR_SHIFT		16
 #define   SPI_FIFO_RD_PTR_MASK		0x7f
 
-static uint8_t spi_read8(uint8_t reg)
-{
-	return read8((void *)(spi_get_bar() + reg));
-}
-
-static uint32_t spi_read32(uint8_t reg)
-{
-	return read32((void *)(spi_get_bar() + reg));
-}
-
-static void spi_write8(uint8_t reg, uint8_t val)
-{
-	write8((void *)(spi_get_bar() + reg), val);
-}
-
-static void spi_write32(uint8_t reg, uint32_t val)
-{
-	write32((void *)(spi_get_bar() + reg), val);
-}
-
 static void dump_state(const char *str, u8 phase)
 {
 	u8 dump_size;
diff --git a/src/soc/amd/common/block/spi/fch_spi_util.c b/src/soc/amd/common/block/spi/fch_spi_util.c
new file mode 100644
index 0000000000..7bac99191a
--- /dev/null
+++ b/src/soc/amd/common/block/spi/fch_spi_util.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/lpc.h>
+#include <amdblocks/spi.h>
+#include <arch/mmio.h>
+#include <assert.h>
+#include <stdint.h>
+
+static uintptr_t spi_base;
+
+void spi_set_base(void *base)
+{
+	spi_base = (uintptr_t)base;
+}
+
+uintptr_t spi_get_bar(void)
+{
+	if (ENV_X86 && !spi_base)
+		spi_set_base((void *)lpc_get_spibase());
+	ASSERT(spi_base);
+
+	return spi_base;
+}
+
+uint8_t spi_read8(uint8_t reg)
+{
+	return read8((void *)(spi_get_bar() + reg));
+}
+
+uint16_t spi_read16(uint8_t reg)
+{
+	return read8((void *)(spi_get_bar() + reg));
+}
+
+uint32_t spi_read32(uint8_t reg)
+{
+	return read32((void *)(spi_get_bar() + reg));
+}
+
+void spi_write8(uint8_t reg, uint8_t val)
+{
+	write8((void *)(spi_get_bar() + reg), val);
+}
+
+void spi_write16(uint8_t reg, uint16_t val)
+{
+	write16((void *)(spi_get_bar() + reg), val);
+}
+
+void spi_write32(uint8_t reg, uint32_t val)
+{
+	write32((void *)(spi_get_bar() + reg), val);
+}