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Age
Commit message (
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Author
2021-02-11
soc/amd/cezanne: select soc-specific ACPI functionality
Felix Held
2021-02-10
soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
Felix Held
2021-02-10
soc/amd/cezanne: Add SPI registers
Raul E Rangel
2021-02-09
soc/amd/cezanne: Enable early LPC support in bootblock stage
Zheng Bao
2021-02-05
soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges
Felix Held
2021-02-05
soc/amd/cezanne/fch: add ACPI I/O port setup
Felix Held
2021-02-03
soc/amd/cezanne: remove UART2/3 AOAC device offsets
Felix Held
2021-01-31
soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 stepping
Felix Held
2021-01-29
soc/amd/cezanne: add empty ramstage FCH support
Felix Held
2021-01-22
soc/amd/cezanne: add pci_devs.h
Felix Held
2021-01-14
soc/amd/cezanne: add AOAC support
Felix Held
2021-01-14
soc/amd/cezanne: add console UART support
Felix Held
2020-12-18
soc/amd/cezanne: Add SMI support
Zheng Bao
2020-12-17
soc/amd/cezanne: add GPIO definitions
Felix Held
2020-12-13
soc/amd/cezanne: add caching setup in bootblock
Felix Held
2020-12-11
soc/amd/cezanne: add 0xcf9 reset
Felix Held
2020-12-09
soc/amd/cezanne: add basic early FCH initialization to bootblock
Felix Held
2020-12-09
soc/amd/cezanne: add common SMBus code to build
Felix Held
2020-12-05
soc/amd/cezanne: add skeleton for new SoC
Felix Held