diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-28 23:40:52 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-29 22:57:01 +0000 |
| commit | 230dbd6d3c194d9f839d31a0a579ef99befdd097 (patch) | |
| tree | 67ee11f634a24c5afa539027f700637c8029a1b4 /src/soc/amd/cezanne/include | |
| parent | faaafb4db121f4413718a7fa1fd771530097e662 (diff) | |
soc/amd/cezanne: add empty ramstage FCH support
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/include')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 2a294e96ef..6949fa57b3 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -30,9 +30,12 @@ /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT (1 << 7) /* Write-once */ -void enable_aoac_devices(void); -void wait_for_aoac_enabled(unsigned int dev); void fch_pre_init(void); void fch_early_init(void); +void fch_init(void *chip_info); +void fch_final(void *chip_info); + +void enable_aoac_devices(void); +void wait_for_aoac_enabled(unsigned int dev); #endif /* AMD_CEZANNE_SOUTHBRIDGE_H */ |