summaryrefslogtreecommitdiff
path: root/src/soc/amd/cezanne/acpi
AgeCommit message (Collapse)Author
2023-09-19soc/amd/cezanne,common: expose eMMC device in ACPI when enabledFelix Held
When the eMMC MMIO device is enabled in the devicetree, it needs to be exposed in ACPI in order for the OS driver to be able to attach to it. The Cezanne eMMC controller isn't used in google/guybrush, so this the code path where the eMMC MMIO device is enabled in the devicetree can't be easily tested. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69ff79b2d1c6a08cf333a2bb3996931962c2c102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-06soc/amd: correctly report I2C controller state in ACPIFelix Held
Instead of reporting all I2C controllers in the system as enabled in the corresponding ACPI device's _STA method, report the I2C devices that are disabled in the devicetree as disabled in the corresponding _STA method too. This is done by returning the contents of the STAT variable inside each device's scope in the DSDT that have a default value of 0 (device not present/disabled). For all enabled and hidden I2C devices i2c_acpi_fill_ssdt gets called which then writes 0xf (device enabled and visible) or 0xb (device enabled, but hidden) to the STAT name inside the same scope, but in the SSDT. This object in the SSDT will then override the default in the DSDT resulting in the _STA method returning the correct status of each device. The code was inspired by commit 7cf9c7451808 ("soc/amd/*: Fix UART ACPI device status"). TEST=On Mandolin all I2C controllers are disabled and with this patch none shows up in the Windows 10 device manager. When enabling an I2C controller in the devicetree for testing, it shows up again in the Windows device manager. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4cd9f447ded3a7f0b092218410c89767ec517417 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-09soc/amd/*: Fix UART ACPI device statusMatt DeVillier
Prior to commit d1c0f958d198 ("acpi: Call acpi_fill_ssdt() only for enabled devices"), uart_inject_ssdt() was used to set the ACPI status (_STA) for both enabled and disabled devices. The aforementioned commit limited it to being called only on enabled devices, which left disabled devices without any _STA method at all -- which the OS assumes means that the device is present and enabled. To fix this, create the _STA method in the UART asl code for each port, and set the return value to a name variable (STAT) which defaults to 0 (not present/disabled). Then, have uart_inject_ssdt() set STAT to present and enabled (0xF) for UARTs actually present on the board. TEST=build/boot google/skyrim (frostflow), dump ACPI tables, and verify that _STA returns 0xF only for UARTs enabled in devicetree. Change-Id: Id89e74c3ea7f53280935898ee35311b7cf3b152a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77092 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-07soc/amd/*/globalnvs,nvs: remove deprecated & unused CBMC field from GNVSFelix Held
Commit cde4f3b2790d ("acpi/gnvs.c: Drop unused pointer to the cbmem console") removed writing the coreboot memory console pointer to the GNVS and kept the CBMC field as reserved. Since those fields aren't needed any more and there are no dependencies on the absolute position of the different fields in GNVS as long as both GNVS definitions on the C and the ASL side match, remove the deprecated and unused CBMC field from the GNVS structs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iadfaf5a4ec1401b027dbfb6a7c6ce74a1dcecdfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/76351 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-06-07soc/amd/cezanne/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75592 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/cezanne/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-13soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide MISC deviceFelix Held
Don't set bit 2 of the return value of the _STA method in order for Windows not to show a warning about an unknown device in the device manager for this device. TEST=The unknown device with device instance path ACPI\AMD0040\3 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If005f06843956004c281fd70cf364171148cb9ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/amd/*/acpi/mmio.asl,sb_fch.asl: change AAHB's _STA back to methodFelix Held
Commit 396fb3db74db ("soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB device") didn't only change the visibility of the device, but also changed the _STA method to a name. While this worked, the specification says that _STA is supposed to be a method, so change it back to being a method. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0932b2875aaf563a4dbd860bdd11a04272e3780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75169 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08soc/amd/*/acpi/northbridge,pci0: don't hide PCI0 root device from OSFelix Held
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates that the device should be shown in the user interface. This ports commit c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS") forward from Stoneyridge to the newer AMD SoCs. TEST=On Mandolin the PCI Express Root Complex now shows up in the device manager on Windows 10 and when switching the view to 'devices by connection', all PCI(e) devices are shown below it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-06soc/amd/cezanne: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Cezanne SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-01-20soc/amd/cezanne: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4034e959d167fb1e08ee5b15e21fb93bc89db8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72093 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-29soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB deviceFelix Held
Don't set bit 2 in _STA in order for Windows not to show a warning about an unknown device in the device manager for this device. Since the _STA object just returns a constant, a name definition can be used instead of a method definition. TEST=The unknown device with device instance path ACPI\AAHB0000\0 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Just shutting down and then booting it again won't clear some internal state in Windows, so a reboot is needed instead for the change to become visible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-14acpi/soc: Conditionally include dptc.aslTim Van Patten
Conditionally include dptc.asl based on the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim TEST=Build majolica Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12soc/amd: Refactor DPTC Tablet ModeTim Van Patten
Refactor AMD DPTC tablet mode in preparation for adding low/no battery DPTC settings. 1. Refactor and simplify acpigen_write_alib_dptc() into the following functions: - acpigen_write_alib_dptc_default() - acpigen_write_alib_dptc_tablet() 2. Add device tree register value dptc_tablet_mode_enable to control whether DPTC tablet mode is enabled for a variant. 3. Add dptc.asl to perform the necessary ACPI checking before modifying the DPTC settings. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Boot skyrim Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-17soc/amd/common/block/i2c: Add support for shared TPM_I2C controllerJan Dabros
There are platforms equipped with AMD SoC where I2C3 controller connected to TPM device is shared between X86 and PSP. In order to handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends acquire and release requests to be accepted by PSP. An example of implementation within Linux kernel is available [1]. There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated driver on OS side can bind to it and handle this special setup. Since PSP takes care of I2C controller power management, we need to remove PowerResource object from DSDT. BUG=b:204508404 BRANCH=guybrush [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17src/soc: Remove space before tabElyes Haouas
Spaces before tabs are not allowed. Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-18soc/amd/cezanne/acpi: Add support for RTC workaroundRaul E Rangel
The RTC on Cezanne is an unstable wake source when the system is in S0i3. We instead need to use an internal timer that triggers a GPIO that acts as a wake source. This change provides the ACPI necessary to allow the OS to manage the wake source. BUG=b:209705576 TEST=Boot guybrush with this patch and several OS patches. Verified the OS sets the correct wake bit, the system correctly suspends and resumes, and the wake source is correctly accounted for. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1f14d14df5d30d48d244416f2ec8c10ac5c8040e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Limonciello <mario.limonciello@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-20soc/amd/cezanna/acpi/mmio.asl: enable ACPI AOAC for I2CJulian Schroeder
This enables runtime power management for the I2C controllers. BUG=b:182556027, b:183983959 TEST=enable dynamic debug in kernel and check i2c D3/D0 transitions during suspend_stress_test. Change-Id: Ia6b9ca95d751f32b7cd701494377f15091c22d2f Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56462 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20soc/amd/cezanne/acpi/mmio: uncomment AOAC_DEVICE macro for UARTsFelix Held
This enables runtime power management for the UART controllers. BUG=b:183983959 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e57d6312feda459cec65f330c6d2072774d4eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-12soc/amd/cezanne/acpi: Change GPIO controller interrupt to sharedRaul E Rangel
The Majolica UEFI ACPI tables have this listed as shared. It's already a level interrupt, so no reason it shouldn't be shared. This change makes it so Windows can correctly initialize the GPIO controller. BUG=b:186212501 TEST=Boot guybrush to windows and see GPIO controller functional. Also boot guybrush to windows and verify GPIO controller still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-06-16soc/amd/cezanne/acpi/mmio: use AOAC offset definesFelix Held
Even though the code is currently commented out, replace the magic numbers with the existing defines. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0dbbadf71f2e5a4d23ee998e2aa0a8b67205845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-09soc/amd/cezanne: Generate PCI routing tableRaul E Rangel
Use the new acpigen_write_PRT to write the _PRT for each PCI bridge. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-08soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB callFelix Held
BUG=b:187212773, b:185481298 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2cf50257d767525d682602cdcc5547bf001fe2ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/53921 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/{cezanne,common}/acpi: Add _OSC methodRaul E Rangel
The linux kernel requires a valid _OSC method. Otherwise the _LPI table is ignored. See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/acpi/bus.c;l=324 Before this patch: acpi_processor_get_lpi_info: LPI is not supported After this patch: acpi_processor_evaluate_lpi: ACPI: \_SB_.CP00: ACPI: Found 4 power states BUG=b:178728116 TEST=Boot OS and verify _LPI table is parsed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I44e554b9db6f70fdd1559105cdaee53aeb2bfbf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-20soc/amd/{common,cezanne}: Add uPEP deviceRaul E Rangel
The uPEP device is required to support S0i3. The device has been written in ASL to make it easier to read and maintain. The device constraints are purely informational. We use a dummy constraint like the Intel platforms to keep both linux and Windows functional. In order for this device to be used by the linux kernel the ACPI_FADT_LOW_PWR_IDLE_S0 flag must be set. So including it unconditionally doesn't cause any problems. The AMD Modern Standby BIOS Implementation Guide defines two UUIDs, one for getting the device constraints, and one for handling notifications. This differs from the Intel specification and the linux driver implementation. For this reason I haven't implemented any of the notification callbacks yet. BUG=b:178728116 TEST=Boot OS and verify _DSM is called: [ 0.226701] lps0_device_attach: ACPI: \_SB_.PEP_: _DSM function mask: 0x3 [ 0.226722] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: _DSM function 1 eval successful [ 0.226723] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list begin: [ 0.226724] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list end Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2deef47eabe702efe1a0f3747c9f27bcec37464b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52445 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30soc/amd/cezanne: Comment the AOAC register accessKarthikeyan Ramasubramanian
Causing the AOAC register access as part of system suspend (S3) causes the suspend procedure to be stuck. Comment it for now to unblock entering S3 and collecting the power numbers. BUG=b:181766974 TEST=Build and boot to OS in Majolica. Enter S3 through "echo mem > /sys/power/state". Change-Id: Ie93bbe393b209b784b9a2257f3916b29d84b25d1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51926 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/amd/cezanne/acpi/soc.asl: Include sleepstates.aslRaul E Rangel
Needed to get the _SX ASL methods. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6323ba413a21d9d867727dbb28340e6df807c86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/amd/cezanne: Move globalnvs.asl to the correct locationMathew King
BUG=b:180507937 TEST=guybrush builds without globalnvs in dsdt.asl Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3ffe94f7b575126e61245bed9c9560313df2d725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51291 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25soc/amd/cezanne/acpi: Add globalnvs.aslRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I53290226012d9f6c08c6adae0a633c7fd5702135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-25soc/amd/cezanne/acpi/pci0.asl: Add LPC deviceRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22soc/amd/cezanne/acpi: Add pci0.aslRaul E Rangel
This differs slightly from picasso. The PCI BAR region is between TOM1 and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms are doing. It also matches what linux derives from the e820 tables: > [mem 0xd0000000-0xf7ffffff] available for PCI devices Picasso currently declares the region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. TEST=Boot majolica and check logs pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff] pci_bus 0000:00: root bus resource [bus 00-3f] Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ff02012795e2166e3a4197071b1136727089318 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/amd/cezanne/acpi/soc.asl: Add platform.aslRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22soc/amd/cezanne/acpi: Add MMIO devicesRaul E Rangel
The devices were copied from picasso with the following modifications: * UART{2,3} were deleted * I2C{0,1} were added * eMMC was removed since it hasn't been validated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-13soc/amd/cezanne/acpi: Add plain soc.aslRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I227cdb7cb4848d1d26f6d7fa13ac2cc1aea08d1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-16 12:56:27 +0000