diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-05-31 16:08:42 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:18:28 +0000 |
| commit | 9adc33d0d080f11db33ecc7fb25be93c8507c36f (patch) | |
| tree | b48da7b00ab6dd9ca3b0e171ba1c4af699b6dcc8 /src/soc/amd/cezanne/acpi | |
| parent | e4b65cc945bb5256fdb65041b9f4d20c05155cd8 (diff) | |
soc/amd/cezanne/chip: use common data fabric domain resource code
Use the new common AMD code that gets the usable non-fixed MMIO windows
from the data fabric MMIO decode registers and generate the PCI0 _CRS
ACPI code based on those regions. For a more detailed description see
the corresponding patch that changes the Picasso code to use this new
code. In contrast to the Picasso code, this change will drop the
unneeded _STA method inside the PCI0 scope which wasn't present in
Picasso's ACPI code before it got replaced by the SSDT that gets
generated by amd_pci_domain_fill_ssdt.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd/cezanne/acpi')
| -rw-r--r-- | src/soc/amd/cezanne/acpi/pci0.asl | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl index fb02a02c3b..c778578823 100644 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ b/src/soc/amd/cezanne/acpi/pci0.asl @@ -3,15 +3,6 @@ Device(PCI0) { Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - External(TOM1, IntObj) /* Generated by root_complex.c */ - - Method(_BBN, 0, NotSerialized) { - Return(0) /* Bus number = 0 */ - } - - Method(_STA, 0, NotSerialized) { - Return(0x0f) /* Status is visible */ - } /* Operating System Capabilities Method */ Method(_OSC, 4) { @@ -26,57 +17,6 @@ Device(PCI0) { Return (Arg3) } } - Name(CRES, ResourceTemplate() { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00ff, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0cf7, /* range maximum */ - 0x0000, /* translation */ - 0x0cf8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0d00, /* range minimum */ - 0xffff, /* range maximum */ - 0x0000, /* translation */ - 0xf300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) - - Method(_CRS, 0) { - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ - MM1B = TOM1 - Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS - Local0 -= TOM1 - MM1L = Local0 - - CreateWordField(CRES, ^PSB0._MAX, BMAX) - CreateWordField(CRES, ^PSB0._LEN, BLEN) - BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 - BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ /* 0:14.3 - LPC */ #include <soc/amd/common/acpi/lpc.asl> |