soc/amd/cezanne: clean up global NVS

From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4034e959d167fb1e08ee5b15e21fb93bc89db8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72093
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 4 insertions, 9 deletions

diff --git a/src/soc/amd/cezanne/acpi/globalnvs.asl b/src/soc/amd/cezanne/acpi/globalnvs.asl
index 6dd1e6bd2a..bccce09678 100644
--- a/src/soc/amd/cezanne/acpi/globalnvs.asl
+++ b/src/soc/amd/cezanne/acpi/globalnvs.asl
@@ -8,13 +8,8 @@
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	,	8,	// 0x00 - Processor Count
-	LIDS,	8,	// 0x01 - LID State
-	,	8,	// 0x02 - AC Power State
-	CBMC,	32,	// 0x03 - 0x06 - coreboot Memory Console
-	PM1I,	64,	// 0x07 - 0x0e - System Wake Source - PM1 Index
-	GPEI,	64,	// 0x0f - 0x16 - GPE Wake Source
-	TMPS,	8,	// 0x17 - Temperature Sensor ID
-	TCRT,	8,	// 0x18 - Critical Threshold
-	TPSV,	8,	// 0x19 - Passive Threshold
+	LIDS,	8,	// 0x00 - LID State
+	CBMC,	32,	// 0x01 - 0x04 - coreboot Memory Console
+	PM1I,	64,	// 0x05 - 0x0c - System Wake Source - PM1 Index
+	GPEI,	64,	// 0x0d - 0x14 - GPE Wake Source
 }