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path: root/src/soc/amd/cezanne/Kconfig
AgeCommit message (Collapse)Author
2021-01-31soc/amd/cezanne/Kconfig: select common PSP gen2 supportFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6068e8b9eb210ce4907fda09208e66e380842de Reviewed-on: https://review.coreboot.org/c/coreboot/+/50152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/cezanne/Kconfig: move selections in alphabetical orderFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99ac82b717e5efb6521040e88a3cfa5f09910be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50010 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/cezanne: compress FSP binaries in CBFSFelix Held
Compressing the FSP binaries in CBFS reduces the load time. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0faf9a3937e4a5027eba6327a51060025971450f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49951 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27soc/amd/cezanne: Add UCODE firmware to CBFSZheng Bao
Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-24soc/amd/cezanne/Kconfig: select missing SSE2 optionFelix Held
This will set the corresponding enable bit in CR4 in bootblock_crt0.S Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc/amd/cezanne/Kconfig: select X86_AMD_FIXED_MTRRSFelix Held
This option will make the ramstage MTRR core set the additional bits in the fixed MTRRs that need to be set on AMD CPUs to enable caching. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94bca61acfc6e38a6d808eb5020537b4e8596178 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc,vendorcode/amd/cezanne: add basic FSP integrationFelix Held
This is a trimmed-down version of the Cezanne FSP integration code, so for example the UPD definitions are empty, which will be addressed later. Since coreboot just leaves the UPD values at their default, this is not a problem during the initial platform bring-up. Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc/amd/cezanne: Add PSP integration for cezanneZheng Bao
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16Felix Held
Change-Id: I97c73324900a0677165afa3f5b182a336d534968 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-01-20soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGEFelix Held
This adds interrupt handlers that end up calling x86_exception(). Change-Id: I3dce539b6f1ef300cf16f20224744a75100f60b8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18ACPI: Select ACPI_SOC_NVS only where suitableKyösti Mälkki
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-01-14soc/amd/cezanne: add AOAC supportFelix Held
Change-Id: I9d7574b60640eaf9a47a797e823324edeaf1e770 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-14soc/amd/cezanne: add console UART supportFelix Held
Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11soc/amd/cezzane: Add a minimal chipset treeFurquan Shaikh
This change adds a minimal chipset tree with only two devices: 1. Domain 2. GNB root complex This allows sconfig to generate the config structure for SoC root device that is used by config_of_soc(). Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-01-10ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki
Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-18soc/amd/cezanne: add GPIO supportFelix Held
This still uses the common GPIO code that supports setting up SMI/SCI support for the GPIOs in all stages, which will get removed in future patches, so for now the SoC's gpio.c needs to be included in all stages. Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-18soc/amd/cezanne: Add SMI supportZheng Bao
Change-Id: I83b9a91cbab297d032292997a4d5768b89fe97dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48645 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11soc/amd/cezanne: add 0xcf9 resetFelix Held
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd/cezanne: add common SMBus code to buildFelix Held
Since the IOAPIC in the FCH gets set up in the SMBus code, also select IOAPIC in Kconfig. Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd: Remove Kconfig BOOTBLOCK_ADDRKyösti Mälkki
Due the location of X86_RESET_VECTOR, the anchor point for linking the bootblock is at the end, which equals ROMSTAGE_ADDR. Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09soc/amd: Remove Kconfig X86_RESET_VECTORKyösti Mälkki
The architectural requirement is for the address to be located at the end of bootblock -0x10 bytes, so the definition was redundant with other Kconfig variables. Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09soc/amd/cezanne: select common ACPIMMIO blockFelix Held
Change-Id: I7f7d11d84733a43500b0135e565d91fe5c493279 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-06soc/amd/cezanne: use common TSC and monotonic timer codeFelix Held
Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48306 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05soc/amd/cezanne: add skeleton for new SoCFelix Held
This is based on the minimal example code in soc/example/min86 and was adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF support. In its current state this won't even reach the boot block, but will pass the build bot. The missing parts for that will be added in future patches. This is an attempt to not go the usual route to create a copy of a previous SoC generation and the make changes to the code to work for the new SoC, but to start from a nearly empty directory and then add the actual code stage by stage and component by component. Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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