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authorFelix Held <felix-coreboot@felixheld.de>2021-01-14 01:40:50 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-01-24 18:15:46 +0000
commit8d0a609e6d1bfb48de781e7223f73ff979d0ce2e (patch)
treed3f40d275aeff99da11287de34bcc1bb62f7a2d6 /src/soc/amd/cezanne/Kconfig
parent45b0714c89db4487074e87ada13b9886c43d9ccd (diff)
soc,vendorcode/amd/cezanne: add basic FSP integration
This is a trimmed-down version of the Cezanne FSP integration code, so for example the UPD definitions are empty, which will be addressed later. Since coreboot just leaves the UPD values at their default, this is not a problem during the initial platform bring-up. Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
-rw-r--r--src/soc/amd/cezanne/Kconfig8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index ecdba5e6a6..15a40377cd 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -16,6 +16,7 @@ config SOC_SPECIFIC_OPTIONS
select HAVE_CF9_RESET
select IDT_IN_EVERY_STAGE
select IOAPIC
+ select PLATFORM_USES_FSP2_0
select RESET_VECTOR_IN_RAM
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
@@ -27,6 +28,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART
+ select UDK_2017_BINDING
config CHIPSET_DEVICETREE
string
@@ -92,6 +94,12 @@ config FSP_M_SIZE
help
Sets the size of DRAM allocation for FSP-M in linker script.
+config FSP_TEMP_RAM_SIZE
+ hex
+ default 0x40000
+ help
+ The amount of coreboot-allocated heap and stack usage by the FSP.
+
config RAMBASE
hex
default 0x10000000