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path: root/src/northbridge
AgeCommit message (Expand)Author
2012-07-25More descriptive error messages in Sandybridge raminit codeStefan Reinauer
2012-07-24ELOG: Fix boot count increment for non-wake caseDuncan Laurie
2012-07-24Ivybridge: fix workaround and enable PAIRDuncan Laurie
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
2012-07-24Make ACPI code detect Sandy/Ivy Bridge dynamicallyStefan Reinauer
2012-07-24Drop (empty) sandybridge_late_initialization()Stefan Reinauer
2012-07-24Add support for HM70 and NM70 LPC bridgeStefan Reinauer
2012-07-24Print PCI ID of PCH during boot upStefan Reinauer
2012-07-24Drop leading spaces from CPU name stringStefan Reinauer
2012-07-24Fix MRC cache update delaysStefan Reinauer
2012-07-24SandyBridge: Add another PCI device ID for northbridgeWalter Murphy
2012-07-24Fixes to enable RC6 on IvyBridgeDuncan Laurie
2012-07-22i945: Disable IGD if plugin VGA is preferredPatrick Georgi
2012-07-22Trinity wrapper code improvement.zbao
2012-07-20Fix udelay() implementation for i945 romstageNico Huber
2012-07-20Drop VGA_BRIDGE_SETUP config optionPatrick Georgi
2012-07-20Intel SCH northbridge: fix resource indexKyösti Mälkki
2012-07-16Drop invalid device ops on Agesa northbridgeKyösti Mälkki
2012-07-16AMD: Fix GFXUMA with 4GB or more RAMKyösti Mälkki
2012-07-16Move setup_uma_memory() to K8 northbridgeKyösti Mälkki
2012-07-16Move setup_uma_memory() to AMDFAM10 northbridgeKyösti Mälkki
2012-07-16Move setup_uma_memory() to Agesa Family14 northbridgeKyösti Mälkki
2012-07-16Move setup_uma_memory() to Agesa Family12 northbridgeKyösti Mälkki
2012-07-16Move setup_uma_memory() to Agesa Family15 northbridgeKyösti Mälkki
2012-07-16Define global uma_memory variablesKyösti Mälkki
2012-07-16Add global uma_resource()Kyösti Mälkki
2012-07-16i5000: Fix resource allocationSven Schnelle
2012-07-09i5000: reset system if raminit failsSven Schnelle
2012-07-06i5000: Add PCI ids for all i5000 flavoursSven Schnelle
2012-07-06i945: Reset IGD on bootPatrick Georgi
2012-07-03AGESA F15 wrapper for Trinityzbao
2012-06-21Don't use 64-bit constant 0x100000000 in linker scriptsNico Huber
2012-06-20i5000: fix another typoSven Schnelle
2012-06-20i5000: fix typosSven Schnelle
2012-06-18i5000: enforce hard resetSven Schnelle
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
2012-05-11Hook up MRC cache updateStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-05-08Some more #if cleanupPatrick Georgi
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
2012-05-02Make Intel i5000 specific options only appear on i5000 systemsStefan Reinauer
2012-05-02Strip quotes from Sandybridge MRC blobStefan Reinauer
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
2012-05-01Update Ivybridge GT power meter tablesDuncan Laurie
2012-05-01Update ivybridge graphics initializationDuncan Laurie
2012-05-01Only send ME Dram Init Done message on SandybridgeDuncan Laurie
2012-05-01Modify DMI init for IvyBridgeVincent Palatin
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
2012-04-30Sandybridge: Temporarily disable MRC cache finding codeStefan Reinauer
2012-04-30Add default map_oprom_vendev() for AMD Family 14h processors.Martin Roth
2012-04-28Reverse Vendor ID & Device ID for map_oprom_vendev()Martin Roth
2012-04-27SMM: Add udelay on Sandybridge systemsStefan Reinauer
2012-04-21Intel e7505: build as separate object fileKyösti Mälkki
2012-04-21Intel e7505: enable ECC scrubbingKyösti Mälkki
2012-04-20Refactor some alignment handlingPatrick Georgi
2012-04-19Intel e7505: refactor onlyKyösti Mälkki
2012-04-17Intel e7505: handlers for undocumented registersKyösti Mälkki
2012-04-16S3 code in coreboot public folder.zbao
2012-04-12Unify IO APIC address specificationPatrick Georgi
2012-04-11Intel e7505: cleanupsKyösti Mälkki
2012-04-11Intel e7505: renames onlyKyösti Mälkki
2012-04-05amdfam10: add phenom II as known cpuBernhard Urban
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
2012-03-27Add the support for RDC R8610 NorthbridgeRudolf Marek
2012-03-16Fix AMD Fam15 CBMEM allocationStefan Reinauer
2012-03-16Fix AMD Fam12 CBMEM allocationStefan Reinauer
2012-03-16Fix AMD Fam10 CBMEM allocationStefan Reinauer
2012-03-16AMD Agesa: delete no-op bootblock filesKyösti Mälkki
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
2012-03-16Fix AMD Agesa leaking KconfigKyösti Mälkki
2012-03-16Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki
2012-03-16VIA southbridge K8T890: Apply un-written naming rulesKyösti Mälkki
2012-03-16Fix AMD Fam14 cbmen allocationMarc Jones
2012-03-15Clean up whitespace in fam14 northbridge.cMarc Jones
2012-03-07Move C labels to start-of-linePatrick Georgi
2012-03-02Fix ECC disable option for AMD Fam10 DDR2 and DDR3.Marc Jones
2012-02-17Avoid ../../.. paths in ASL filesPatrick Georgi
2012-02-17Rename i945 ACPI files to not carry an i945_ prefixPatrick Georgi
2012-02-17Remove whitespace.Patrick Georgi
2012-02-16AGESA F15: AGESA family15 model 00-0fh northbridge wrapperKerry Sheh
2012-02-16RD890: AMD RD890/SR56X0 CIMX wrapperKerry Sheh
2012-02-10Remove non-existent includeSven Schnelle
2012-02-10i5000: halt second BSPSven Schnelle
2012-02-02Add Intel i5000 Memory Controller HubSven Schnelle
2012-01-31northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig optionPeter Stuge
2012-01-26Make Geode GX2 VGA setup work.Nils Jacobs
2012-01-10i945: fix tsc udelay()Sven Schnelle
2012-01-07Update geode GX2 tree to match LX.Nils Jacobs
2012-01-05Clean up AMD Fam14 SSDTMarc Jones
2011-12-31White space and coding style fixes.Nils Jacobs
2011-12-14k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-xFlorian Zumbiehl
2011-12-02Change AMD vendorcode buildKyösti Mälkki
2011-11-23k8 raminit: fix bug, improve clock selection, add clock limit for sock754Florian Zumbiehl
2011-11-16fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminitFlorian Zumbiehl
2011-11-07Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26Florian Zumbiehl
2011-11-01remove trailing whitespaceStefan Reinauer
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