remove trailing whitespace

Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

25 files changed, 26 insertions, 26 deletions

diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h
index e6f9d81b83..e6f9d81b83 100755..100644
--- a/src/northbridge/amd/agesa/family10/amdfam10.h
+++ b/src/northbridge/amd/agesa/family10/amdfam10.h
diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c
index f6ae8be8b9..f6ae8be8b9 100755..100644
--- a/src/northbridge/amd/agesa/family10/bootblock.c
+++ b/src/northbridge/amd/agesa/family10/bootblock.c
diff --git a/src/northbridge/amd/agesa/family10/chip.h b/src/northbridge/amd/agesa/family10/chip.h
index c0ac56e5a9..c0ac56e5a9 100755..100644
--- a/src/northbridge/amd/agesa/family10/chip.h
+++ b/src/northbridge/amd/agesa/family10/chip.h
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index b3e4c63d00..b3e4c63d00 100755..100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
diff --git a/src/northbridge/amd/agesa/family10/northbridge.h b/src/northbridge/amd/agesa/family10/northbridge.h
index 0530ee7495..0530ee7495 100755..100644
--- a/src/northbridge/amd/agesa/family10/northbridge.h
+++ b/src/northbridge/amd/agesa/family10/northbridge.h
diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h
index 5b24f2d63a..5b24f2d63a 100755..100644
--- a/src/northbridge/amd/agesa/family10/reset_test.h
+++ b/src/northbridge/amd/agesa/family10/reset_test.h
diff --git a/src/northbridge/amd/agesa/family10/root_complex/chip.h b/src/northbridge/amd/agesa/family10/root_complex/chip.h
index 15a2e1ae69..15a2e1ae69 100755..100644
--- a/src/northbridge/amd/agesa/family10/root_complex/chip.h
+++ b/src/northbridge/amd/agesa/family10/root_complex/chip.h
diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
index 6ec4da9c9f..6ec4da9c9f 100755..100644
--- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c
+++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c
diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c
index eead31d26b..f6ae8be8b9 100755..100644
--- a/src/northbridge/amd/agesa/family12/bootblock.c
+++ b/src/northbridge/amd/agesa/family12/bootblock.c
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
diff --git a/src/northbridge/amd/agesa/family12/chip.h b/src/northbridge/amd/agesa/family12/chip.h
index 462610d6ea..462610d6ea 100755..100644
--- a/src/northbridge/amd/agesa/family12/chip.h
+++ b/src/northbridge/amd/agesa/family12/chip.h
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 55109b57be..2c039d2b4e 100755..100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -311,7 +311,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
         }
 
 #if 0
-        // We need to double check if there is speical set on base reg and limit reg 
+        // We need to double check if there is speical set on base reg and limit reg
             // are not continous instead of hole, it will find out it's hole_startk
         if(mem_hole.node_id==-1) {
             resource_t limitk_pri = 0;
@@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
             }
         }
 #endif
-        
+
         return mem_hole;
 }
 #endif
@@ -471,7 +471,7 @@ static void set_resources(device_t dev)
     struct resource *res;
 
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resources - Start.\n");
- 
+
     /* Find the nodeid */
     nodeid = amdfam12_nodeid(dev);
 
@@ -782,7 +782,7 @@ static void domain_enable_resources(device_t dev)
   /* Must be called after PCI enumeration and resource allocation */
 //  printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - Start.\n");
   printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - Start.\n");
-//  val = agesawrapper_amdinitmid (); 
+//  val = agesawrapper_amdinitmid ();
 //  if(val) {
 //    printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
 //  }
@@ -819,7 +819,7 @@ static void cpu_bus_set_resources(device_t dev)
     pci_dev_set_resources(dev);
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_set_resources - End.\n");
 }
- 
+
 static void cpu_bus_init(device_t dev)
 {
     u32 val;
@@ -830,20 +830,20 @@ static void cpu_bus_init(device_t dev)
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - Start.\n");
-    sb_After_Pci_Init (); 
+    sb_After_Pci_Init ();
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - Start.\n");
-    sb_Mid_Post_Init (); 
+    sb_Mid_Post_Init ();
     printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - End.\n");
 #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
 
     /* Must be called after PCI enumeration and resource allocation */
     printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - Start.\n");
-    val = agesawrapper_amdinitmid (); 
+    val = agesawrapper_amdinitmid ();
     if(val) {
         printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
     }
diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h
index 8de80ff501..8de80ff501 100755..100644
--- a/src/northbridge/amd/agesa/family12/northbridge.h
+++ b/src/northbridge/amd/agesa/family12/northbridge.h
diff --git a/src/northbridge/amd/agesa/family12/root_complex/chip.h b/src/northbridge/amd/agesa/family12/root_complex/chip.h
index 91599252fc..91599252fc 100755..100644
--- a/src/northbridge/amd/agesa/family12/root_complex/chip.h
+++ b/src/northbridge/amd/agesa/family12/root_complex/chip.h
diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c
index eead31d26b..f6ae8be8b9 100644
--- a/src/northbridge/amd/agesa/family14/bootblock.c
+++ b/src/northbridge/amd/agesa/family14/bootblock.c
@@ -20,7 +20,7 @@
  * ***************************************************************************
  *
  */
- 
+
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index b410bb96d6..99518065de 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -958,7 +958,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
 //           byte 1 - fid_max
 //           byte 2 - nb_cof_vid_update
 //           byte 3 - apic id
-   
+
 #define LAPIC_MSG_REG 0x380
 #define F10_APSTATE_STARTED 0x13  // start of AP execution
 #define F10_APSTATE_STOPPED 0x14  // allow AP to stop
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 566e1fbbb0..ccee1fdff0 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -292,8 +292,8 @@
 #define CUR_PSTATE_MSR 0xc0010063
 #define TSC_FREQ_SEL_SHIFT 24
 
-#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) 
- 
+#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
+
 #define  WAIT_PSTATE_TIMEOUT 80000000  /* 0.1 s , unit : 1.25 ns */
 
 #endif
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 8b50eed790..a262686f87 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -673,7 +673,7 @@ static void setup_uniprocessor(void)
 }
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
-static int optimize_connection_group(const u8 *opt_conn, int num) 
+static int optimize_connection_group(const u8 *opt_conn, int num)
 {
 	int needs_reset = 0;
 	int i;
@@ -1709,7 +1709,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
 		}
 #endif
 
-		
+
 #if CONFIG_K8_REV_F_SUPPORT == 0
 		/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
 		if (!is_cpu_pre_b3())
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 4533818ef8..7ba2b90406 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -48,7 +48,7 @@ static void mcf3_read_resources(device_t dev)
 	}
 
 	iommu = 1;
-	if( get_option(&iommu, "iommu") < 0 ) 
+	if( get_option(&iommu, "iommu") < 0 )
 	{
 		iommu = CONFIG_IOMMU;
 	}
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index a62036621f..319293b7ed 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1815,7 +1815,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 #endif
 #endif
 	];
-	
+
 	if (bios_cycle_time > min_cycle_time) {
 		min_cycle_time = bios_cycle_time;
 	}
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index d2bef3868e..ae1537f24c 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -140,7 +140,7 @@
 #define BU_CFG2		0xC001102A
 
 /*
- * Processor package types 
+ * Processor package types
  */
 #define AMD_PKGTYPE_FrX_1207 0
 #define AMD_PKGTYPE_AM3_2r2 1
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index f7c6b5af25..37b138a6da 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -196,7 +196,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
 			}
 
 			mbi_header = (mbi_header_t *)&mbi[i];
-			len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16); 
+			len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
 
 			if (obj_header->objnum == count) {
 #ifdef DEBUG_SMI_I82830
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 85ba1be4f0..23c3cb14d1 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -831,12 +831,12 @@ static void spd_set_dram_throttle_control(void)
 	 */
 	dtc_reg |= (3 << 28);
 
-	/* Read Counter Based Power Throttle Control (RCTC): 
+	/* Read Counter Based Power Throttle Control (RCTC):
 	 *   0 = 85%
 	 */
 	dtc_reg |= (0 << 24);
 
-	/* Write Counter Based Power Throttle Control (WCTC): 
+	/* Write Counter Based Power Throttle Control (WCTC):
 	 *   0 = 85%
 	 */
 	dtc_reg |= (0 << 20);
@@ -879,7 +879,7 @@ static void spd_update(u8 reg, u32 new_value)
 	u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);
 	PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
 #endif
-}	
+}
 
 /* if ram still doesn't work do this function */
 static void spd_set_undocumented_registers(void)
@@ -967,7 +967,7 @@ static void sdram_set_spd_registers(void)
 	if (dimm_mask == 0) {
 		print_debug("No usable memory for this controller\n");
 	} else {
-		PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);	
+		PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
 
 		spd_set_row_attributes(dimm_mask);
 		spd_set_dram_controller_mode(dimm_mask);
diff --git a/src/northbridge/via/cx700/northbridge.h b/src/northbridge/via/cx700/northbridge.h
index 4ae9ce5937..c651bfe5f2 100644
--- a/src/northbridge/via/cx700/northbridge.h
+++ b/src/northbridge/via/cx700/northbridge.h
@@ -21,6 +21,6 @@
 #define NORTHBRIDGE_VIA_CX700_H
 
 extern unsigned int cx700_scan_root_bus(device_t root, unsigned int max);
-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0)));
 #endif				/* NORTHBRIDGE_VIA_CX700_H */
diff --git a/src/northbridge/via/vt8623/northbridge.h b/src/northbridge/via/vt8623/northbridge.h
index 9c0828741c..176a590490 100644
--- a/src/northbridge/via/vt8623/northbridge.h
+++ b/src/northbridge/via/vt8623/northbridge.h
@@ -2,7 +2,7 @@
 #define NORTHBRIDGE_VIA_VT8623_H
 
 unsigned int vt8623_scan_root_bus(device_t root, unsigned int max);
-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0)));
 
 #endif /* NORTHBRIDGE_VIA_VT8623_H */
diff --git a/src/northbridge/via/vx800/northbridge.h b/src/northbridge/via/vx800/northbridge.h
index 05f75d2649..4b51bb7c11 100644
--- a/src/northbridge/via/vx800/northbridge.h
+++ b/src/northbridge/via/vx800/northbridge.h
@@ -21,7 +21,7 @@
 #define NORTHBRIDGE_VIA_VX800_H
 
 extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max);
-extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0)));
 
 #endif				/* NORTHBRIDGE_VIA_VX800_H */