summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/x4x
AgeCommit message (Expand)Author
2019-09-28nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ useKyösti Mälkki
2019-09-28nb/intel/x4x: Avoid x4x.h header with romcc-bootblockKyösti Mälkki
2019-09-24intel/cpu: Switch older models to TSC_MONOTONIC_TIMERKyösti Mälkki
2019-09-06nb/intel/x4x/raminit: Move dummy reads after JEDEC initArthur Heymans
2019-08-28intel/smm/gen1: Use smm_subregion()Kyösti Mälkki
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
2019-08-15intel/smm/gen1: Rename header fileKyösti Mälkki
2019-08-15arch/x86: Add postcar_frame_common_mtrrs()Kyösti Mälkki
2019-08-15cpu/intel: Refactor platform_enter_postcar()Kyösti Mälkki
2019-08-15cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
2019-08-08lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki
2019-08-07northbridge/intel: Rename ram_calc.c to memmap.cKyösti Mälkki
2019-08-03intel/i945,gm45,pineview,x4x: Fix stage cache locationKyösti Mälkki
2019-08-03intel/i945,gm45,pineview,x4x: Move stage cache support functionKyösti Mälkki
2019-07-17nb/intel/x4x: Die on invalid memory speedsJacob Garber
2019-07-09cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki
2019-07-04arch/x86: Adjust size of postcar stackKyösti Mälkki
2019-06-21nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps}Elyes HAOUAS
2019-06-05nb/intel/x4x: Remove variable set but not usedElyes HAOUAS
2019-06-04nb/intel/x4x/rcven.c: Remove variable set but not usedElyes HAOUAS
2019-05-29src/northbridge: Add missing 'include <types.h>'Elyes HAOUAS
2019-05-24nb/northbridge/intel/x4x/acpi.c: Remove variable set but not usedElyes HAOUAS
2019-05-23nb/intel/x4x/early_init.c: Remove variable set but not usedElyes HAOUAS
2019-05-15src/northbridge: Remove unneeded include <arch/io.h>Elyes HAOUAS
2019-05-07{gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() functionElyes HAOUAS
2019-04-29nb/x4x: Use system_reset() and full_reset()Elyes HAOUAS
2019-04-25src/northbridge/intel: Remove unused variablesElyes HAOUAS
2019-04-11nb/intel/{gm45,i945,x4x}: Correct array bounds checksJacob Garber
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
2019-03-27Move calls to quick_ram_check() before CBMEM initKyösti Mälkki
2019-03-21{northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem()Subrata Banik
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
2019-03-16src: Drop unused '#include <halt.h>'Elyes HAOUAS
2019-03-13nb/intel/stage_cache.c: Drop unnecessary includesElyes HAOUAS
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-06Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
2019-02-01sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read()Kyösti Mälkki
2019-01-24nb/intel/x4x: Put stage cache in TSEGArthur Heymans
2019-01-23nb/intel/x4x: Use parallel MP initArthur Heymans
2019-01-13nb/intel/x4x: Remove spurious pcidev_on_root() usageNico Huber
2019-01-10mb: Move timestamp_add_now to northbridge x4xElyes HAOUAS
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
2019-01-04device: Replace ugly cases of dev_find_slot()Kyösti Mälkki
2018-12-19northbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
2018-12-18northbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
2018-12-03nb/intel/x4x: Use common code for SMM in TSEGArthur Heymans
2018-11-19src: Add required space after "switch"Elyes HAOUAS
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-05nb/intel/x4x/raminit: Add missing spaceJonathan Neuschäfer
2018-10-24nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardwareArthur Heymans
2018-10-24nb/intel/*: Account for cbmem_top alignmentArthur Heymans
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-10-15nb/intel/x4x: Fix P45 CAPID max frequencyArthur Heymans
2018-10-15nb/intel/x4x: Program read training results to all ranksArthur Heymans
2018-10-08src: Use tabs for indentationElyes HAOUAS
2018-09-16nb/intel/x4x: Don't use cached settings if CPU FSB has been changedArthur Heymans
2018-09-05nb/intel/x4x/gma.c: fix skipping of native graphics initStefan Tauner
2018-08-22nb/intel/*/gma.c: Skip NGI when VGA decode is not enabledArthur Heymans
2018-08-10src: Fix typoElyes HAOUAS
2018-08-09src/northbridge: Fix typoElyes HAOUAS
2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-08-01nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 20:32:58 +0000