coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-02-16	nb/intel: Add missing <types.h>	Elyes HAOUAS
2021-01-30	nb/intel/x4x: Define and use MMCONF_BUS_NUMBER	Angel Pons
2020-09-21	src/northbridge: Drop unneeded empty lines	Elyes HAOUAS
2020-08-04	nb/intel/x4x: Define and use `HOST_BRIDGE` macro	Angel Pons
2020-08-04	nb/intel/x4x: Refactor `decode_pcie_bar`	Angel Pons
2020-08-04	nb/intel/x4x: Change signature of `decode_pciebar`	Angel Pons
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-05	src/northbridge: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-17	src (minus soc and mainboard): Remove copyright notices	Patrick Georgi
2020-02-24	src: capitalize 'RAM'	Elyes HAOUAS
2019-11-01	lib/cbmem_top: Add a common cbmem_top implementation	Arthur Heymans
2019-08-28	intel/smm/gen1: Use smm_subregion()	Kyösti Mälkki
2019-08-26	soc/intel: Use common romstage code	Kyösti Mälkki
2019-08-22	arch/x86: Add <arch/romstage.h>	Kyösti Mälkki
2019-08-15	intel/smm/gen1: Rename header file	Kyösti Mälkki
2019-08-15	arch/x86: Add postcar_frame_common_mtrrs()	Kyösti Mälkki
2019-08-15	cpu/intel: Refactor platform_enter_postcar()	Kyösti Mälkki
2019-08-07	northbridge/intel: Rename ram_calc.c to memmap.c	Kyösti Mälkki