nb/intel/x4x: Define and use MMCONF_BUS_NUMBER

Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.

Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 36 deletions

diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index aa737f391f..5114e0bc3e 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -57,42 +57,6 @@ u32 decode_tseg_size(const u32 esmramc)
 	}
 }
 
-int decode_pcie_bar(u32 *const base, u32 *const len)
-{
-	*base = 0;
-	*len = 0;
-
-	const struct {
-		u16 num_buses;
-		u32 addr_mask;
-	} busmask[] = {
-		{256, 0xf0000000},
-		{128, 0xf8000000},
-		{64,  0xfc000000},
-		{0,   0},
-	};
-
-	const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO);
-
-	if (!(pciexbar_reg & 1)) {
-		printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
-		return 0;
-	}
-
-	const u32 index = (pciexbar_reg >> 1) & 3;
-	const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
-	const int max_buses = busmask[index].num_buses;
-
-	if (!pciexbar) {
-		printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
-		return 0;
-	}
-
-	*base = pciexbar;
-	*len = max_buses << 20;
-	return 1;
-}
-
 static size_t northbridge_get_tseg_size(void)
 {
 	const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC);