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2024-05-07dram/ddr3: Use the same naming convention as DDR4Elyes Haouas
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07device/dram/ddr{3,4}: Rename spd_raw_data for specific DDRElyes Haouas
Rename different spd_raw_data[] for DDR3 and DDR4. This is to solve the conflict when we include both "ddr3.h" and ddr4.h" for example here: src/device/dram/spd.c. Otherwise, it won't compile as DDR3 and DDR4 have different spd_raw_data[] size. Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-13sandybridge,haswell,broadwell: Use DIV_ROUND_CLOSEST macroAngel Pons
Integer division in C truncates toward zero. When the dividend and the divisor are positive, one can add half of the divisor to the dividend to round the division result towards the closest integer. We already have a macro in commonlib to do just that, so put it to good use. Tested with BUILD_TIMELESS=1, coreboot images for the Asus P8Z77-V LX2 and the Asrock B85M Pro4 do not change. Change-Id: I251af82da15049a3a2aa6ea712ae8c9fe859caf6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52651 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12nb/intel/sandybridge/raminit: Add tCPDED corner casePatrick Rudolph
tCPDED is always 1, except for steppings earlier than Sandy Bridge D0. Reduces the differences to MRC.bin. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79762 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-12nb/intel/sandybridge/raminit: Only write register on Ivy BridgePatrick Rudolph
Only write register WMM_READ_CONFIG on Ivy Bridge as it's reserved on Sandy Bridge. Tested on Lenovo X220: Still boots and runs fine. Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79761 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-12nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNBPatrick Rudolph
MRC.bin doesn't write BANDTIMERS_SNB register, so drop the write. The bits written were targeting a reserved range, so assume it didn't do anything useful. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I920aabd60831c791188af976914553787cc0ff18 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-11tree: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-07nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG to match MRC.binPatrick Rudolph
A register dump between native and MRC.bin raminit showed a difference in the PM_DLL_CONFIG register. Use the same value as MRC.bin uses. Tested on Lenovo X220: Still boots and works fine. Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79759 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-02lib: Move IP checksum to commonlibJulius Werner
This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24northbridge: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iddac15cc42532f44dda44032be0f8525f6347abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80070 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-05northbridge/intel/sandybridge: Enable x86_64 for mrc.binPatrick Rudolph
Enable x86_64 support for MRC.bin: - Add a wrapper function for console printing that calls into long mode to call native do_putchar - Remove Kconfig guard for x86_64 when MRC is being used Tested: Booted Lenovo X220 using mrc.bin under x86_64 and MRC is able to print to the console. Change-Id: I21ffcb5f5d4bf155593e8111531bdf0ed7071dfc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-04nb/intel/sandybridge/raminit: Honor SPD's dll_off_modePatrick Rudolph
In DDR3 DLL-Off mode is an optional feature advertised by SPD. Honor the SPD and only use DLL-Off mode when all DIMMs on the same channel indicate support for it. The same is done on MRC.bin. Tested on Lenovo X220: Still boots fine. Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79758 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-03northbridge/intel/sandybridge/raminit: Prepare MRC path for x86_64Patrick Rudolph
- Remove pointers in argument list passed to MRC to make sure the struct has the same size on x86_64 as on x86_32. - Add assembly wrapper to call the MRC with argument in EAX. - Wrap calling MRC in protected_mode_call_2arg, which is a stub on x86_32 Tested: Boots on Lenovo X220 using MRC in x86_32 and x86_64 mode. Change-Id: Id755e7381c5a94360e3511c53432d68b7687df67 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-23nb/intel/{gm45,sandybridge}: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: I64361262e5b16419351fa139c8fdf04c5c07662d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-06sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetreeFelix Held
Since the EHCI controllers in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the EHCI device operations to the PCI devices during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d Reviewed-on: https://review.coreboot.org/c/coreboot/+/79171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-06sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetreeFelix Held
Since the XHCI controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the XHCI device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79170 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-06sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetreeFelix Held
Since the PCI bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the PCI bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79169 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetreeFelix Held
Since the SMBus controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the SMBus device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79168 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-05sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetreeFelix Held
Since the LPC bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the LPC bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-04nb/intel/sandybridge/pcie: drop unneeded HAVE_ACPI_TABLES guardsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e8c8b3e3672d1589a5910753986e4033d2ce766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-20nb/intel/sandybridge: Use SA devid to identify PC typePatrick Rudolph
Instead of using MSR IA32_PLATFORM_ID read the SystemAgent device id to figure out the PC type. This follows the BWG which suggest to not use MSR IA32_PLATFORM_ID for system identification. Tested: Lenovo X220 still boots. Change-Id: Ibddf6c75d15ca7a99758c377ed956d483abe7ec1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78826 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-11-20nb/intel/sandybridge: Fix unitialized variable issueJeremy Compostella
commit 1e9601c5ef80 ("nb/intel/sandybridge: Standardize MRC vs. native SPD mapping API") introduced an uninitialized variable issue. Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539 Found-by: Coverity CID 1524317 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetreeFelix Held
Since the HD audio controller in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and audio still works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetreeFelix Held
Since the PCIe root ports in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are visible and working. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18nb/intel/sandybridge: assign gma ops in chipset devicetreeFelix Held
Since the integrated GPU is always function 0 of device 2 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux and graphics works in UEFI Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79114 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18nb/intel/sandybridge: assign host bridge ops in chipset devicetreeFelix Held
Since the host bridge is always function 0 of device 0 on bus 0, the device operations can be statically assigned in the devicetree and there's no need to bind the host bridge device operations to the PCI device during runtime via a list of PCI IDs. TEST=Lenovo X220 still boots to Linux Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79113 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-14nb/intel/sandybridge: Drop raminit_native.hKeith Hui
After commit adaeb1102186 (nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration), no boards use this header anymore and it no longer offers original content. Adjust northbridge code #includes as needed and drop it. Change-Id: I2785e920bd6188dbfc1a6157351083ec4a2526d0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-13nb/intel/sandybridge: Clean up post Haswell SPD mapping API migrationKeith Hui
With migration to Haswell SPD mapping interface complete: 1. Remove weak stubs meant to ensure smooth transition and internalizes mainboard_get_spd() within raminit.c. 2. Remove post-mainboard SPD data sanitization code in raminit_mrc.c, now that it fills its own SPD data. 3. Remove old prototypes from raminit_native.h 4a. Drops raminit_native.h from raminit.c, as individual headers therein are already included. 4b. Drop another header from raminit.c IWYU identified as unneeded. asus/p8z77-m still builds afterwards. (sandybridge to receive a full IWYU cleanup later.) Change-Id: Ie073c1386cd0a645069f0e1416263b4fa359b74b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76991 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13nb/intel/sandybridge: Standardize MRC vs. native SPD mapping APIKeith Hui
Changes both MRC and native raminit code path to get SPD mapping from one place. Boards with all memory socketed specify their mappings in a devicetree setting introduced in commit 5709e03613b3 ("nb/intel/sandybridge: Migrate MRC settings to devicetree") back in May 2019 but remains unused as of this patch. This setting will now hold raw SMBus addresses, and MRC raminit gets code to translate them into a representation MRC expects. Boards with soldered down memory (specifically with HAVE_SPD_IN_CBFS in their board Kconfig), with or without socketed memory, specify their layouts in mb_get_spd_map() as used by Haswell boards, where they access hardware GPIO straps to select which SPD data to use. This harmonizes the way boards specify their SPD layouts across Haswell/SNB/IVB boards whether using MRC or native raminit. Going forward they only need to specify the layout in one place. (Going forward the devicetree setting should be backported to Haswell, once we get native raminit working there.) With this, northbridge code is now fully responsible for loading all SPD data, be it from CBFS or SMBus. To avoid breakage, transition will happen in stages: 1. This patch gets all the code in, and implements weak stubs that maintain existing code and data flow (i.e. mainboards still populate final SPD layout data). At this point devicetree already uses new representation, but is still unused meaning no breakage. 2. Follow-up patch(es) remove mainboard_get_spd() from mainboards, and replace it with mb_get_spd_map() or devicetree values (as appropriate) with converted SPD info. The "weak" mainboard_get_spd() with new logic takes over. Boards go Haswell Style at this point. Boards with MRC raminit also lose code to fill in SPD data, allowing new data to take hold. 3. Clean-up patch removes the weak functions and public prototypes re mainboard_get_spd(), making it internal to northbridge. Changeover is complete. Change-Id: I1a75279d981e46505930a9ce1aae894ccc4e1f24 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76965 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20x86: Add pre-memory stages CBFS cache scratchpad supportJeremy Compostella
Having a CBFS cache scratchpad offers a generic way to decompress CBFS files through the cbfs_map() function without having to reserve a per-file specific memory region. This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set the pre-memory stages CBFS cache size. A cache size of zero disables the CBFS cache feature. The default value is 16 KB which seems a reasonable minimal value enough to satisfy basic needs such as the decompression of a small configuration file. This setting can be adjusted depending on the platform needs and capabilities. We have set this size to zero for all the platforms without enough space in Cache-As-RAM to accommodate the default size. TEST=Decompression of vbt.bin in romstage on rex using cbfs_map() Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-10-20device/device.h: Rename pci_domain_scan_busArthur Heymans
On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-09-11nb/intel: Remove space between function name and '('Elyes Haouas
Change-Id: Ibffaf86f9e32d747c8f2f7a3643df8935fb00047 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-13nb/intel/sandybridge: Clarify RAM overclock optionsAngel Pons
Rewrite them to more accurately describe what they are about. Change-Id: Icb0ac1e592b662bbb81da431ff97af1a00f952c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-09treewide: Get rid of "NO_DDRx" selectionElyes Haouas
Change-Id: I8fa26e7a398eee855c31a76f0f89b4111368c2a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-01nb/sandybridge: Remove redundant include of "ddr3.c"Elyes Haouas
It is already selected here device/dram/Makefile.inc Change-Id: I32a1ecc4e0f90725f9356158ce2978502b590d5c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76390 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-20acpi: Move ECAM resource below PNP0C02 device in a common placeArthur Heymans
From the Linux documentation (Documentation/PCI/acpi-info.rst): [6] PCI Firmware 3.2, sec 4.1.2: If the operating system does not natively comprehend reserving the MMCFG region, the MMCFG region must be reserved by firmware. The address range reported in the MCFG table or by _CBA method (see Section 4.1.3) must be reserved by declaring a motherboard resource. For most systems, the motherboard resource would appear at the root of the ACPI namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources in this case should not be claimed in the root PCI bus’s _CRS. The resources can optionally be returned in Int15 E820 or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource. So in order for the OS to use ECAM MMCONF over legacy PCI IO configuration, a PNP0C02 HID device needs to reserve this region. As no AMD platform has this defined in DSDT this fixes Linux using legacy PCI IO configuration over MMCONF. Tianocore messes with e820 table in such a way that it prevents Linux from using PCIe ECAM. This change fixes that problem. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-23nb/intel/snb: Abolish mainboard_should_reset_usb()Keith Hui
Of the 13 mainboards that implement mainboard_should_reset_usb() hook, all but one do the same: Stop MRC from resetting USB when resuming from S3 suspend. This hook turns out is only here to facilitate a USB reset workaround on samsung/stumpy for an old ChromeOS kernel which is no longer needed. Drop the workaround, the hook, and headers no longer used. roda/rv11/early_init.c is left with no useful code after this patch, so drop it entirely from both bootblock and romstage. Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-04mb/*: Replace SNB PCI devices with references from chipset.cbArthur Heymans
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-02nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hwBill XIE
Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries. This can restore s3 resume capability for Sandy Bridge platforms lost after commit d165357ec37c ("sb,soc/intel: Use register_new_ioapic_gsi0()"). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-04spd.h: Move enum ddr3_module_type to ddr3.hElyes Haouas
Move specific enum ddr3_module_type to <device/dram/ddr3.h>. Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-04nb/intel/*/Kconfig: Remove dummy NORTHBRIDGE_SPECIFIC_OPTIONSElyes Haouas
Change-Id: Icecef272bd4cd2a204c903783787bbec751fe9e5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-26nb/intel/sandybridge/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas
Change-Id: I75bc048d9e04be8d0cab25f6aad1c71d3e7a4008 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71506 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22nb/intel/sandybridge/raminit_common.h: Add needed <device/dram/ddr3.h>Elyes Haouas
Change-Id: I059e94ef46fdc959a6e37365eb335409698b987a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15nb/intel/sandybridge/sandybridge.h: Remove unnecessary guardElyes Haouas
__ACPI__ is covered through __ASSEMBLER__. Change-Id: I6a637e63c6bbe4af7cd52be1893e47d6b5967886 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70697 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-06nb/intel/sandybridge: Use read{8,32}p()Elyes Haouas
Change-Id: I3bbb2f02a2dc182956deffc554a6b161a93ad963 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-06nb/intel/sandybridge: Use write32p()Elyes Haouas
Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-01cpu/intel/model_206ax: Remove fake lapic deviceArthur Heymans
Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic device is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-01cpu/intel/sandybridge: Use enum for ACPI C statesArthur Heymans
Also remove the now unnecessary comments from the devicetree. Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-30nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetreeArthur Heymans
Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30nb/intel/sandybridge: Add a chipset devicetreeArthur Heymans
This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/northbridge: Remove unnecessary space after castsElyes Haouas
Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas
Get rid of a lot of casts. Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-17nb/intel/ironlake,sandybridge/gma: Fix out() parameter orderKyösti Mälkki
Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-04nb/intel/sandybridge: Specify supported memory typesElyes Haouas
Change-Id: Ie43e818d03f411733e1bba5b7a4721c9a54ff4a4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-14nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6d0d945011fa046b974c6f4554cb9fb15e523afb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67578 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26nb/intel/sandybridge: Align TOUUD down to 1 MiB granularityArthur Heymans
This register has a 1MiB granularity. The lowest bit is a lock bit. Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17commonlib/clamp.h: Relicense file to be BSD-compatibleAngel Pons
I added this header in commit a6c8b4becbd12fe6043557ca1e398c1a7c691007 (nb/intel/sandybridge: Rewrite get_FRQ). Relicense it as "BSD-3-Clause OR GPL-2.0-or-later" and move it into the BSD-licensed commonlib part. Change-Id: I89ebdcdf8d06e78e624e37a443696981b3b17b7d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66711 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-17nb/intel/sandybridge/raminit_mrc.c: Use semicolon instead of commaElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I15d7e2f30b054d14009761006a2f89f45e001118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-30nb/intel: Drop local legacy_hole definitionsKyösti Mälkki
These are architectural and followup works will address the VGA MMIO and/or ASEG better. Change-Id: I88e1dca8058661e31ba934b9860751e13a107108 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55928 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13nb/intel/snb/raminit_mrc.c: Remove set but unused variableArthur Heymans
Change-Id: I1cf656b404b0e880c061b273ef259ca40a6d499a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-20nb/intel/snb: Reduce scope of functionsArthur Heymans
Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-10nb/intel/sandybridge: Restore `mainboard_early_init()` callAngel Pons
Commit 7a874330919a4df9cc5b66058b4340465b7ea041 (mb/google,samsung: Drop init_bootmode_straps()) got rid of the `mainboard_early_init()` function call and weak definition in Sandy Bridge code. However, this function is still used by several Sandy Bridge mainboards, so bring back the dropped call and weak definition. The aforementioned commit did not cause any build-time errors because it did not remove the `mainboard_early_init()` function declaration. Change-Id: I82768e9a187696d42b61be44d4aa048acc19d551 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-09mb/google,samsung: Drop init_bootmode_straps()Kyösti Mälkki
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-28nb/intel/sandybridge/acpi: Support setting PCI bars above 4GArthur Heymans
Although coreboot can allocate resources above 4G, Linux does not consider those allocation valid when there is no region above 4G in _CRS and disables the device. TESTED: x220 with and external GPU via the expresscard slot. Linux does not touch the BARs allocated above 4G. Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-05cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMERKyösti Mälkki
Leftover from using UDELAY_LAPIC on these platforms. Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macrosElyes HAOUAS
Change-Id: Icca870d1c97a2737dec3f31b0f2e4c3222c711ae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macroElyes HAOUAS
Change-Id: Ibbb6e6d44b1415b18aa59310f4d36d61b9a2a080 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macrosElyes HAOUAS
Use macros defined in <smbios.h> for 'ddr_type' and 'bus_width' Change-Id: I0501147139387cd9b5c7ec6b7ba7f8a5c5bd18bb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-10src/{northbridge,southbridge}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I1205b1a27436853f2187d8ddd95f0bf9a853f986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-05src/northbridge: Remove unused <delay.h>Elyes HAOUAS
Change-Id: I5449feeb65c49c79bc7657a1c3777a0f128a13b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-30northbridge/intel/sandybridge/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I58c2545c881572127b6d34b5527c5d4bd7d97dfb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-02nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXTMichał Żygowski
Initialize the DPR register and check if SCLEAN needs to be run. Allows to reliably boot the platform if ungraceful shutdown occured or the memory controller has been locked by TXT. TEST=Dell OptiPlex 9010 with Intel TXT enabled boots successfully after 4s power button override or power cable unplug when SENTER was executed. Successfully boot QubesOS 4.0 with TBoot v1.8.2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-26nb/intel/sandybridge: Add support for DPRMichał Żygowski
Include DPR in the memory map calculations if enabled. DPR is required for Intel TXT support. TEST=Boot Debian 10 and see the DPR memory being reserved in E820 and cbmem logs: "BIOS-e820: [mem 0x000000007fc09000-0x00000000829fffff] reserved" "TSEG base 0x80000000 size 8M" "DPR base 0x7fd00000 size 3M" Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04nb/intel: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I617fea8a09049e9a87130640835ea6c3e2faec60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-18ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki
As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-11nb/intel/sandybridge: Populate meminfo when using MRCMatt DeVillier
Populate a memory_info struct with PEI and SPD data, in order to inject the CBMEM_INFO table necessary to populate a type17 SMBIOS table. On Broadwell, this is done by the MRC binary, but the older Sandy Bridge MRC binary doesn't populate the pei_data struct with all the info needed, so we have to pull it from the SPD. Some values are hardcoded based on platform specifications. Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16MRC platforms: Fix MRC version printk format specifiersAngel Pons
The printed values are unsigned, and should be printed accordingly. Change-Id: Ie5edce914c389c70460b1ed3390731e3568340dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-15nb/intel/sandybridge: Add x86_64 supportPatrick Rudolph
Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper. Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64 Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-27lib/hexdump: remove hexdump32 and use hexdump insteadFelix Held
hexdump and hexdump32 do similar things, but hexdump32 is mostly a reimplementation that has additional support to configure the console log level, but has a very unexpected len parameter that isn't in bytes, but in DWORDs. With the move to hexdump() the console log level for the hexdump is changed to BIOS_DEBUG. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6138d17f0ce8e4a14f22d132bf5c64d0c343b80d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54925 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-05nb/intel: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21nb/intel: Use get_int_option()Angel Pons
Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-10nb/intel: Replace remaining BAR accessorsAngel Pons
These changes are not reproducible for some reason. Change-Id: I43b445b8af8871db87fb86747db8a35cec75716a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51867 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel/sandybridge: Use new fixed BAR accessorsAngel Pons
One instance in northbridge.c breaks reproduciblity when changed. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I2148183827bcacc9e6edb91b26ad35eb2dae5090 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51866 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10nb/intel: Factor out remaining MCHBAR macrosAngel Pons
Except for some formatting differences, the macros are equivalent. Change-Id: I5dc4f115b0873fb96683263ecd152d3d1504647d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51863 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05nb/intel/sandybridge: Drop `pci_mmio_size`Angel Pons
There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 22:52:27 +0000