diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-18 18:07:27 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-06 16:20:24 +0000 |
| commit | 903454e7b865b5b3d3a1615372d6eb5974ef4435 (patch) | |
| tree | 0f464e852014a3174e03a50ef592b6dbd53182c4 /src/northbridge/intel/sandybridge | |
| parent | afebab1ebe109c7b9ca9820679a4681b996bce0b (diff) | |
sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree
Since the EHCI controllers in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the EHCI device operations to the
PCI devices during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79171
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chipset.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index c304ab4c81..22a0e7bfb1 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -25,7 +25,7 @@ chip northbridge/intel/sandybridge device pci 16.2 alias me_ide_r off end # Management Engine IDE-R device pci 16.3 alias me_kt off end # Management Engine KT device pci 19.0 alias gbe off end # Intel Gigabit Ethernet - device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 + device pci 1a.0 alias ehci2 off ops bd82x6x_usb_ehci_ops end device pci 1b.0 alias hda off ops bd82x6x_azalia_ops end # High Definition Audio device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end # PCIe Port #1 device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end # PCIe Port #2 @@ -35,7 +35,7 @@ chip northbridge/intel/sandybridge device pci 1c.5 alias pcie_rp6 off ops bd82x6x_pcie_rp_ops end # PCIe Port #6 device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end # PCIe Port #7 device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 - device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 + device pci 1d.0 alias ehci1 off ops bd82x6x_usb_ehci_ops end device pci 1e.0 alias pci_bridge off ops bd82x6x_pci_bridge_ops end device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 |