diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-05-06 11:48:41 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-05-07 10:53:31 +0000 |
| commit | 8bcd8210ea64bdbb35485d361e645f2c9cfcf763 (patch) | |
| tree | 7f36324e0d9e90e03f239974c7ae99220616c6d7 /src/northbridge/intel/sandybridge | |
| parent | 0f45e17f564a657ddf9804124e4e30da0edb1d13 (diff) | |
dram/ddr3: Use the same naming convention as DDR4
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 24 |
2 files changed, 13 insertions, 13 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2a4eae5bd5..8a8bd8310b 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -142,7 +142,7 @@ static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only) { int j; if (id_only) { - for (j = SPD_DIMM_MOD_ID1; j < 128; j++) + for (j = SPD_DDR3_MOD_ID1; j < 128; j++) (*spd)[j] = smbus_read_byte(addr, j); } else { for (j = 0; j < SPD_SIZE_MAX_DDR3; j++) diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index cad86ba51e..8d3c4023c8 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -467,14 +467,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = 0; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], - sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); + &pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM], + sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][SPD_DIMM_PART_NUM], - sizeof(uint8_t) * SPD_DIMM_PART_LEN); + &pei_data->spd_data[0][SPD_DDR3_PART_NUM], + sizeof(uint8_t) * SPD_DDR3_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); + (pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF); dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; @@ -491,14 +491,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = 1; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], - sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); + &pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM], + sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][SPD_DIMM_PART_NUM], - sizeof(uint8_t) * SPD_DIMM_PART_LEN); + &pei_data->spd_data[0][SPD_DDR3_PART_NUM], + sizeof(uint8_t) * SPD_DDR3_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); + (pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF); dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; |