summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/haswell/northbridge.c
AgeCommit message (Expand)Author
2023-07-17nb/haswell: Use newer function for resource declarationsArthur Heymans
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
2022-11-25cpu/intel/haswell: Move chip_ops to cpu clusterArthur Heymans
2022-11-09nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetreeArthur Heymans
2022-10-06treewide: use predicate to check if pci device is on n-th busFabio Aiuto
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
2022-06-24device/resource: Modify some resource allocation instancesKyösti Mälkki
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
2022-03-07src: Make PCI ID define names shorterFelix Singer
2021-12-16Spell *Boot Guard* with a space for official spellingPaul Menzel
2021-11-05nb/intel/haswell/northbridge.c: Drop stale commentAngel Pons
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
2021-06-16nb/intel/haswell/memmap.h: Define MMIO window sizesAngel Pons
2021-04-10nb/intel: Replace remaining BAR accessorsAngel Pons
2021-04-10nb/intel/haswell: Use new fixed BAR accessorsAngel Pons
2021-03-28nb/intel/haswell: Replace `DMIBAR64` and `EPBAR64`Angel Pons
2021-03-10nb/intel/haswell: Finalize northbridge in ramstageAngel Pons
2021-03-07nb/intel/haswell: Indent PCI ops with tabsAngel Pons
2021-03-01nb/intel/haswell: Fix DPR size handlingTim Wawrzynczak
2021-02-24nb/intel/haswell/northbridge.c: Correct DPR handlingAngel Pons
2021-02-18nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG writeAngel Pons
2021-02-16nb/intel: Add missing <types.h>Elyes HAOUAS
2021-02-16nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
2021-02-16nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()Kyösti Mälkki
2021-02-12nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
2021-02-05intel: Turn `DEFAULT_RCBA` into a Kconfig symbolAngel Pons
2021-01-30nb/intel/haswell: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-27nb/intel/haswell/haswell.h: Do not include `pch.h`Angel Pons
2020-10-31{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons
2020-10-24nb/intel/haswell: Generalise northbridge chip nameAngel Pons
2020-10-24nb/intel/haswell: Set up Root Complex topologyAngel Pons
2020-10-15nb/intel/haswell: Account for DPR region in memory mapAngel Pons
2020-08-04nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-03nb/intel/haswell: Add Crystal Well PCI IDsIru Cai
2020-07-31nb/intel/haswell: Configure VCs on Egress PortAngel Pons
2020-07-28nb/intel/haswell: Enable DMI ASPMAngel Pons
2020-06-06src: Use pci_dev_ops_pci where applicableAngel Pons
2020-06-06src: Remove unused '#include <cpu/x86/smm.h>'Elyes HAOUAS
2020-05-12device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-05-08nb/intel/haswell/northbridge.c: Fix typoAngel Pons
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-03-15nb/intel/haswell: Tidy up code and commentsAngel Pons
2019-12-19src/northbridge: Remove unused <stdlib.h>Elyes HAOUAS
2019-12-12nb/{haswell,i945,sandybridge}: Drop outdated commentElyes HAOUAS
2019-08-15cpu/intel: Replace bsp_init_and_start_aps()Kyösti Mälkki
2019-03-21{northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem()Subrata Banik
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
2018-12-29nb/intel/haswell: Handle boards that do not support IGDTristan Corrick
2018-12-29nb/intel/haswell: Use DEVEN to disable devicesTristan Corrick
2018-12-18nb/intel/haswell: Add server processor host bridge device IDIru Cai
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-02nb/intel/haswell: Consolidate memory controller PCI driver structsTristan Corrick
2018-11-01sb/intel/lynxpoint: Automatically generate the ACPI PCI routing tableTristan Corrick
2018-11-01nb/intel/haswell: Add a PCI ID for a desktop memory controllerTristan Corrick
2018-09-25northbridge: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
2018-05-18nb/intel/haswell: Get rid of device_tElyes HAOUAS
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
2018-03-08nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APICMatt DeVillier
2018-03-08nb/intel/haswell: Generate ACPI DMAR tableMatt DeVillier
2017-07-03northbridge/intel/haswell: Fix undefined behaviorRyan Salsamendi
2017-06-27nb/intel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
2017-01-06nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-03-10ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki
2014-11-01northbridge/intel: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
2014-10-11acpi: Remove explicit pointer tracking in per-device ssdt.Vladimir Serbinenko
2014-09-22haswell: Move to per-device ACPIVladimir Serbinenko
2014-02-16haswell: backup the default SMM region on resumeAaron Durbin
2014-01-15CBMEM intel: Define get_top_of_ram() once per chipsetKyösti Mälkki
2013-12-12haswell: Export functions for CPU family+model and steppingDuncan Laurie
2013-12-07haswell: Misc power management setup and fixesDuncan Laurie
2013-10-15CBMEM: Define cbmem_top() just once for x86Kyösti Mälkki
2013-07-10Fix MMCONF_SUPPORT_DEFAULT for ramstageKyösti Mälkki
2013-06-03haswell: fix overflow handling TOUUDAaron Durbin
2013-05-01boot: remove cbmem_post_handling()Aaron Durbin
2013-03-23resources: introduce reserved_ram_resource()Aaron Durbin
2013-03-22haswell: use dynamic cbmemAaron Durbin
2013-03-22coreboot: dynamic cbmem requirementAaron Durbin
2013-03-21haswell: use s3_resume field in romstage_handoffAaron Durbin
2013-03-21haswell: cbmem_get_table_location() implementationAaron Durbin
2013-03-18haswell: fix ACPI MCFG tableAaron Durbin
2013-03-18haswell: enable caching before SMM initializationAaron Durbin
2013-03-17haswell: include TSEG region in cacheable memoryAaron Durbin
2013-03-16haswell: don't add a 0-sized memory range resourceAaron Durbin
2013-03-15haswell: Fix BDSM and BGSM indicies in memory mapAaron Durbin
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 17:38:10 +0000