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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-03-04 01:44:15 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-08 19:14:17 +0000 |
| commit | a51e379eaff3652dc64e23bb0d3784222a38723a (patch) | |
| tree | 5296bfb357dddedc61f585f3bf36c14b351b6044 /src/northbridge/intel/haswell/northbridge.c | |
| parent | 8a6377ec24c85bc6a18eb9c57045746d2261ce1a (diff) | |
nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
GFXVTBAR/VTVC0BAR policy registers set to be consistent with
proprietary vendor firmwares on hardware of same platform
(2 different vendor firmwares compared, found to be identical).
Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24983
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index f51eb35ee8..bbf1604b4c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -290,7 +290,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(device_t dev, int *resource_cnt) { unsigned long base_k, size_k; unsigned long touud_k; @@ -332,7 +332,7 @@ static void mc_add_dram_resources(device_t dev) * The resource index starts low and should not meet or exceed * PCI_BASE_ADDRESS_0. */ - index = 0; + index = *resource_cnt; /* 0 - > 0xa0000 */ base_k = 0; @@ -380,18 +380,31 @@ static void mc_add_dram_resources(device_t dev) CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif + *resource_cnt = index; } static void mc_read_resources(device_t dev) { + int index = 0; + const bool vtd_capable = + !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + /* Read standard PCI resources. */ pci_dev_read_resources(dev); /* Add all fixed MMIO resources. */ mc_add_fixed_mmio_resources(dev); + /* Add VT-d MMIO resources if capable */ + if (vtd_capable) { + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, + GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, + VTVC0_BASE_SIZE / KiB); + } + /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev); + mc_add_dram_resources(dev, &index); } static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) |