index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
User &
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
northbridge
/
intel
/
gm45
/
raminit.c
Age
Commit message (
Expand
)
Author
2019-01-06
device: Use pcidev_path_on_root()
Kyösti Mälkki
2018-11-29
src: Remove duplicated round up function
Elyes HAOUAS
2018-10-24
nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
Arthur Heymans
2018-08-10
src: Fix typo
Elyes HAOUAS
2018-04-04
nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers
Jonathan Neuschäfer
2018-03-28
nb/intel/gm45: Allocate a 8M TSEG region
Arthur Heymans
2017-10-03
nb/intel/gm45: Remove UMA alignment optimization
Nico Huber
2017-06-12
nb/intel/gm45: Add romstage timestamps
Arthur Heymans
2017-04-19
nb/intel/gm45: Hide some output behind DEBUG_RAM_SETUP
Nico Huber
2016-11-28
nb/intel/gm45: Fix panel-power-sequence clock divisor
Nico Huber
2016-11-21
nb/intel: Fix some spelling mistakes in comments and strings
Martin Roth
2016-11-09
nb/intel/gm45: Use LAPIC udelay instead of custom version
Arthur Heymans
2016-06-12
nb/intel/raminit (native): Read PCI mmio size from devicetree
Patrick Rudolph
2015-12-31
nb/intel/gm45: Export low-power and (SFF) options
Nico Huber
2015-10-31
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-05-21
Remove address from GPLv2 headers
Patrick Georgi
2015-02-15
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
Kevin Paul Herbert
2014-08-16
gm45: Decrease MTRR usage
Vladimir Serbinenko
2014-08-12
gm45: Reserve RAM for ME if it's active.
Vladimir Serbinenko
2014-07-29
gm45: Move spd address map to board-specific config.
Vladimir Serbinenko
2014-07-11
src: Make use of 'CEIL_DIV(a, b)' macro across tree
Edward O'Callaghan
2014-07-01
stdlib: Drop duplicates of min() and max()
Kyösti Mälkki
2013-03-22
x86: Unify arch/io.h and arch/romcc_io.h
Stefan Reinauer
2012-11-27
intel/gm45: new northbridge
Patrick Georgi