diff options
| author | Nico Huber <nico.h@gmx.de> | 2017-10-02 20:07:53 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-10-03 19:48:01 +0000 |
| commit | ca3e121607d7cc04dd1da7b2e40d7a4d9fa039bb (patch) | |
| tree | 8b044fccb9d0c24fbd0b5395808375970c354a0b /src/northbridge/intel/gm45/raminit.c | |
| parent | 29922a540922550b80ba76a821c85eae328899cc (diff) | |
nb/intel/gm45: Remove UMA alignment optimization
This code path was only triggered in one corner case: GFX UMA set to
48MiB. It created a hole below UMA to save MTRRs. But, this hole was
never accounted for when calculating cbmem_top(). Instead of trying
to fix it, remove it, it's not worth the trouble.
TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings.
Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/gm45/raminit.c')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d2da3b02ab..a44e3975be 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1241,10 +1241,6 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); uma_sizem = (gms_sizek + gsm_sizek) >> 10; - /* Further reduce MTRR usage if it costs use less than - 16 MiB. */ - if (ALIGN_UP(uma_sizem, 64) - uma_sizem <= 16) - uma_sizem = ALIGN_UP(uma_sizem, 64); } } |