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Author
2011-06-03
This patch sets max freq defaults for ddr2 and ddr3for fam10.
Marc Jones
2011-02-28
Improving BKDG implementation of P-states,
Xavi Drudis Ferran
2011-02-28
Improving BKDG implementation of P-states,
Xavi Drudis Ferran
2010-11-13
MTRR related improvements for AMD family 10h and family 0Fh systems
Scott Duplichan
2010-08-30
Multi-DIMMS on AMD ddr3 MCT channel B works.
Kerry She
2010-08-22
documented workaround erratum 414, see
Xavi Drudis Ferran
2010-08-22
documented workaround erratum 372, see
Xavi Drudis Ferran
2010-07-08
Fix all warnings in the tree
Stefan Reinauer
2010-07-08
get rid of even more fam10 and k8 warnings.
Stefan Reinauer
2010-04-23
DDR3 support for AMD Fam10.
Zheng Bao
2010-04-16
zero warnings days: unify mp tables. fix warnings.
Stefan Reinauer
2010-04-15
Remove a few more warnings from fam10.
Myles Watson
2009-08-24
This patch is about the DA-C2 and RB-C2. Chip with install processor
Zheng Bao
2009-08-19
The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instea...
Zheng Bao
2009-07-01
Add AMD family 10 AM2r2 support.
Zheng Bao
2009-06-06
Fix for Erratum 350 for AMD Fam10h CPUs.
Marco Schmidt
2008-12-05
Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>
Stefan Reinauer
2008-04-11
Bring Fam10 memory controller init up to date with the latest AMD BKDG
Marc Jones (marc.jones
2008-01-18
Please bear with me - another rename checkin. This qualifies as trivial, no
Stefan Reinauer
2007-12-19
Initial AMD Barcelona support for rev Bx.
Marc Jones
