Bring Fam10 memory controller init up to date with the latest AMD BKDG

recomendations.
Changes include the following:
fix > 4GB dqs tests
fix channel interleaving
ecc memory scrub updates
MC tristating updates
debug print changes
fix memory hoisting across nodes -
    The DRAM Hole Address Register is set via devx in each node, but the Node
    number <-> DRAM Base mapping and the Node number <-> DstNode mapping is
    set in Node 0. The memmap is setup on node0 and copied to the other nodes
    later. so dev, not devx. The bug was the hole was always being set on the
    first node.

Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 9 insertions, 4 deletions

diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 481ed86507..93f000de4c 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -129,11 +129,11 @@ u16 mctGet_NVbits(u8 index)
 		//val = 1;	/* enable */
 		break;
 	case NV_BottomIO:
-		val = 0xC0;	/* address bits [31:24] */
+		val = 0xE0;	/* address bits [31:24] */
 		break;
 	case NV_BottomUMA:
 #if (UMA_SUPPORT == 0)
-		val = 0xC0;	/* address bits [31:24] */
+		val = 0xE0;	/* address bits [31:24] */
 #elif (UMA_SUPPORT == 1)
 		val = 0xB0;	/* address bits [31:24] */
 #endif
@@ -205,7 +205,7 @@ u16 mctGet_NVbits(u8 index)
 		val = 1;		/* Enabled */
 		//val = 0;	/* Disabled */
 	case NV_ChannelIntlv:
-		val = 5;	/* Disabled */ /* Not currently checked in mctchi_d.c */
+		val = 5;	/* Not currently checked in mctchi_d.c */
 	/* Bit 0 =     0 - Disable
 	 *             1 - Enable
 	 * Bits[2:1] = 00b - Address bits 6
@@ -336,3 +336,8 @@ u32 mctGetLogicalCPUID_D(u8 node)
 {
 	return mctGetLogicalCPUID(node);
 }
+
+u8 mctSetNodeBoundary_D(void)
+{
+	return 0;
+}