coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2011-01-20	For Cx, each ChipSel need to be sent MR command.	Zheng Bao
2011-01-17	The code is tested on my board with register DIMMs. More tests need to be	Zheng Bao
2011-01-06	Fix some settings fo AMD MCT. It is based on BIOS test suite.	Zheng Bao
2010-12-02	More explicite and straight way to set seed.	Zheng Bao
2010-10-13	Trivial. Clean up code and add some comments.	Zheng Bao
2010-10-09	Trivial. Spell checking.	Zheng Bao
2010-10-09	Trivial. Spell checking.	Zheng Bao
2010-10-08	Trivial. Spell checking.	Zheng Bao
2010-10-08	Trivial. Fix the typo.	Zheng Bao
2010-10-01	Trivial. Re-indent the code.	Zheng Bao
2010-09-28	Trivial. re-Indent the code.	Zheng Bao
2010-09-27	Obviously missing brackets.	Xavi Drudis Ferran
2010-09-21	Fix the typo. Field DisAutoRefresh is in DramTimngHi.	Zheng Bao
2010-09-09	Also improve boot time on AMD for the DDR3 code path.	Arne Georg Gleditsch
2010-09-05	Trivial. Currently the max frequency is preset as 400Mhz. We need to set a	Zheng Bao
2010-09-04	AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.	Kerry She
2010-08-31	Get Byte65/66 for register manufacture ID code. RegMan1Present will	Zheng Bao
2010-08-30	Multi-DIMMS on AMD ddr3 MCT channel B works.	Kerry She
2010-08-30	Trivial syntax correction of AMD mct_ddr3 dir.	Kerry She
2010-08-22	documented workaround erratum 414, see	Xavi Drudis Ferran
2010-08-22	documented workaround erratum 372, see	Xavi Drudis Ferran
2010-04-23	DDR3 support for AMD Fam10.	Zheng Bao