diff options
| author | Zheng Bao <zheng.bao@amd.com> | 2010-10-08 05:08:47 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-10-08 05:08:47 +0000 |
| commit | c3af12fb8a930b8885b1c6c6b35d2aeff155b3c3 (patch) | |
| tree | 9d767c25f010d46f05cc611a02dafc7d5e7f6a49 /src/northbridge/amd/amdmct/mct_ddr3 | |
| parent | 3d682fe8887b2ddd6c3c7e30c13b4e2f1c59779d (diff) | |
Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index fcbc6b3780..53aed58447 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -656,7 +656,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, { /* Initiates a memory clear operation for all node. The mem clr - * is done in paralel. After the memclr is complete, all processors + * is done in parallel. After the memclr is complete, all processors * status are checked to ensure that memclr has completed. */ u8 Node; @@ -868,7 +868,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat, * HW memory clear process that the chip is capable of. The sooner * that dram init is set for all nodes, the faster the memory system * initialization can complete. Thus, the init loop is unrolled into - * two loops so as to start the processeses for non BSP nodes sooner. + * two loops so as to start the processes for non BSP nodes sooner. * This procedure will not wait for the process to finish. * Synchronization is handled elsewhere. */ @@ -1520,7 +1520,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, DramConfigMisc = 0; DramConfigMisc2 = 0; - /* set bank addessing and Masks, plus CS pops */ + /* set bank addressing and Masks, plus CS pops */ SPDSetBanks_D(pMCTstat, pDCTstat, dct); if (pDCTstat->ErrCode == SC_StopError) goto AutoConfig_exit; @@ -1547,7 +1547,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, else val = 6; DramControl &= ~0xFF; - DramControl |= val; /* RdPrtInit = 6 for Cx CPU */ + DramControl |= val; /* RdPtrInit = 6 for Cx CPU */ if (mctGet_NVbits(NV_CLKHZAltVidC3)) DramControl |= 1<<16; /* check */ @@ -1570,7 +1570,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, } if (!(Status & (1 << SB_Registered))) - DramConfigLo |= 1 << UnBuffDimm; /* Unbufferd DIMMs */ + DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */ if (mctGet_NVbits(NV_ECC_CAP)) if (Status & (1 << SB_ECCDIMMs)) @@ -3511,7 +3511,7 @@ static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat, * Silicon Status: Fixed In Rev B0 * * Bug#15880: Determine validity of reset settings for DDR PHY timing. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR3 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR3 training. */ for (Node = 0; Node < 8; Node++) { pDCTstat = pDCTstatA + Node; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index c853b88ff6..953f7470f6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -481,7 +481,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, continue; } - BanksPresent = 1; /* flag for atleast one bank is present */ + BanksPresent = 1; /* flag for at least one bank is present */ TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid); if (!valid) { print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4); |