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Commit message (
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Author
2014-05-23
northbridge/amd/amdmct: Superfluous parenthesis in if-statements
Edward O'Callaghan
2014-05-22
northbridge/amd/amdmct/mct: Initialize variables at the eol
Edward O'Callaghan
2014-01-28
x86: add common definitions for control registers
Aaron Durbin
2013-06-03
northbridge/amd/amdmct: Use `static const` instead of `const static`
Paul Menzel
2013-03-01
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
Paul Menzel
2012-03-02
Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
Marc Jones
2011-10-15
AMD CPU and chipset fixes for compilation with gcc 4.6
Stefan Reinauer
2011-06-03
This patch sets max freq defaults for ddr2 and ddr3for fam10.
Marc Jones
2011-01-20
For Cx, each ChipSel need to be sent MR command.
Zheng Bao
2011-01-17
The code is tested on my board with register DIMMs. More tests need to be
Zheng Bao
2011-01-06
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Zheng Bao
2010-12-02
More explicite and straight way to set seed.
Zheng Bao
2010-10-13
Trivial. Clean up code and add some comments.
Zheng Bao
2010-10-09
Trivial. Spell checking.
Zheng Bao
2010-10-09
Trivial. Spell checking.
Zheng Bao
2010-10-08
Trivial. Spell checking.
Zheng Bao
2010-10-08
Trivial. Fix the typo.
Zheng Bao
2010-10-01
Trivial. Re-indent the code.
Zheng Bao
2010-09-28
Trivial. re-Indent the code.
Zheng Bao
2010-09-27
Obviously missing brackets.
Xavi Drudis Ferran
2010-09-21
Fix the typo. Field DisAutoRefresh is in DramTimngHi.
Zheng Bao
2010-09-09
Also improve boot time on AMD for the DDR3 code path.
Arne Georg Gleditsch
2010-09-05
Trivial. Currently the max frequency is preset as 400Mhz. We need to set a
Zheng Bao
2010-09-04
AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.
Kerry She
2010-08-31
Get Byte65/66 for register manufacture ID code. RegMan1Present will
Zheng Bao
2010-08-30
Multi-DIMMS on AMD ddr3 MCT channel B works.
Kerry She
2010-08-30
Trivial syntax correction of AMD mct_ddr3 dir.
Kerry She
2010-08-22
documented workaround erratum 414, see
Xavi Drudis Ferran
2010-08-22
documented workaround erratum 372, see
Xavi Drudis Ferran
2010-04-23
DDR3 support for AMD Fam10.
Zheng Bao
