| Age | Commit message (Expand) | Author |
|---|---|---|
| 2010-09-09 | Also improve boot time on AMD for the DDR3 code path. | Arne Georg Gleditsch |
| 2010-09-05 | Trivial. Currently the max frequency is preset as 400Mhz. We need to set a | Zheng Bao |
| 2010-09-04 | AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. | Kerry She |
| 2010-08-31 | Get Byte65/66 for register manufacture ID code. RegMan1Present will | Zheng Bao |
| 2010-08-30 | Trivial syntax correction of AMD mct_ddr3 dir. | Kerry She |
| 2010-04-23 | DDR3 support for AMD Fam10. | Zheng Bao |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |