Age | Commit message (Expand) | Author |
2018-10-30 | {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros | Elyes HAOUAS |
2018-10-23 | src: Remove unneeded whitespace | Elyes HAOUAS |
2018-10-18 | cpu/amd: Use common AMD's MSR | Elyes HAOUAS |
2018-06-14 | src: Get rid of unneeded whitespace | Elyes HAOUAS |
2017-01-12 | amd/mct/ddr2: Remove orphaned Tab_TrefT_k variable | Timothy Pearson |
2017-01-10 | amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStruc | Timothy Pearson |
2017-01-04 | amdfam10: Perform major include ".c" cleanup | Damien Zammit |
2016-11-09 | nb/amd/amdmct/mct: Remove commented code | Elyes HAOUAS |
2016-10-04 | src/northbridge: Remove unnecessary whitespace | Elyes HAOUAS |
2016-09-21 | northbridge/amd/amdmct: Improve code formatting | Elyes HAOUAS |
2016-08-31 | northbridge/amd: Add required space before opening parenthesis '(' | Elyes HAOUAS |
2016-08-23 | src/northbridge: Remove unnecessary whitespace before "\n" and "\t" | Elyes HAOUAS |
2015-11-14 | northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables | Timothy Pearson |
2015-11-02 | cpu/amd: Add initial AMD Family 15h support | Timothy Pearson |
2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
2015-10-26 | northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization | Timothy Pearson |
2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
2015-04-01 | northbridge/amd/amdfam10: Collect DIMM information for ramstage use | Timothy Pearson |
2015-03-07 | northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and later | Timothy Pearson |
2015-01-06 | northbridge: Drop print_ implementation from non-romcc boards | Stefan Reinauer |
2014-07-29 | Uniformly spell frequency unit symbol as Hz | Elyes HAOUAS |
2014-05-23 | northbridge/amd/amdmct: Superfluous parenthesis in if-statements | Edward O'Callaghan |
2013-03-01 | GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« | Paul Menzel |
2012-03-02 | Fix ECC disable option for AMD Fam10 DDR2 and DDR3. | Marc Jones |
2011-03-28 | Add AMD C32 support. | Zheng Bao |
2011-01-06 | Fix some settings fo AMD MCT. It is based on BIOS test suite. | Zheng Bao |
2010-10-08 | Trivial. Spell checking. | Zheng Bao |
2010-09-28 | Trivial. re-Indent the code. | Zheng Bao |
2010-09-27 | Obviously missing brackets. | Xavi Drudis Ferran |
2010-09-21 | Complete the code which was missing. | Zheng Bao |
2010-09-09 | Please find appended. This patch gets rid of the %gs magic altogether, | Arne Georg Gleditsch |
2010-09-09 | Also improve boot time on AMD for the DDR3 code path. | Arne Georg Gleditsch |
2010-09-09 | Apparently, it's not crucial to clear this at the exact moment we switch | Arne Georg Gleditsch |
2010-09-04 | AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code. | Kerry She |
2010-04-30 | Get rid of a few more warnings. | Myles Watson |
2010-04-27 | Since some people disapprove of white space cleanups mixed in regular commits | Stefan Reinauer |
2010-04-16 | zero warnings days: unify mp tables. fix warnings. | Stefan Reinauer |
2010-04-15 | Remove a few more warnings from fam10. | Myles Watson |
2010-03-22 | printk_foo -> printk(BIOS_FOO, ...) | Stefan Reinauer |
2009-09-14 | Use the coreboot pci config read/write functions instead of direct cf8/cfc | Marc Jones |
2009-08-25 | Without this patch, if we only got a DIMM in Channel B, memory can not be | Zheng Bao |
2009-06-06 | Fix for Erratum 350 for AMD Fam10h CPUs. | Marco Schmidt |
2008-12-05 | Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de> | Stefan Reinauer |
2008-07-23 | Memory initialization support for AMD Fam10 B3 (B0-B2 already supported). | Marc Jones |
2008-04-11 | Bring Fam10 memory controller init up to date with the latest AMD BKDG | Marc Jones (marc.jones |
2008-01-18 | Please bear with me - another rename checkin. This qualifies as trivial, no | Stefan Reinauer |
2007-12-19 | Initial AMD Barcelona support for rev Bx. | Marc Jones |