northbridge/amd/amdmct: Improve code formatting

Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 117 insertions, 117 deletions

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 16e67dfdf2..87863b143e 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -195,7 +195,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 * 1. Complete Hypertransport Bus Configuration
 	 * 2. SMBus Controller Initialized
 	 * 3. Checksummed or Valid NVRAM bits
-	 * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs
+	 * 4. MCG_CTL=-1, MC4_CTL_EN = 0 for all CPUs
 	 * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to
 	 *     entry
 	 * 6. All var MTRRs reset to zero
@@ -308,7 +308,7 @@ restartinit:
 		MCTMemClr_D(pMCTstat,pDCTstatA);
 	}
 
-	mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) );	// Node 0
+	mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0));	// Node 0
 	print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus);
 	return;
 
@@ -434,7 +434,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 
 				}
 			}
-			for (Channel = 0; Channel<2; Channel++) {
+			for (Channel = 0; Channel < 2; Channel++) {
 				SetEccDQSRcvrEn_D(pDCTstat, Channel);
 			}
 
@@ -452,7 +452,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 				 *   + 0x100 to next dimm
 				*/
 				for (DIMM = 0; DIMM < 2; DIMM++) {
-					if (DIMM==0) {
+					if (DIMM == 0) {
 						index = 0;	/* CHA Write Data Timing Low */
 					} else {
 						if (pDCTstat->Speed >= 4) {
@@ -461,7 +461,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 							break;
 						}
 					}
-					for (Dir=0;Dir<2;Dir++) {//RD/WR
+					for (Dir = 0; Dir < 2; Dir++) {//RD/WR
 						p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir];
 						val = stream_to_int(p); /* CHA Read Data Timing High */
 						Set_NB32_index_wait(dev, index_reg, index+1, val);
@@ -474,12 +474,12 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 				}
 			}
 
-			for (Channel = 0; Channel<2; Channel++) {
+			for (Channel = 0; Channel < 2; Channel++) {
 				reg = 0x78 + Channel * 0x100;
 				val = Get_NB32(dev, reg);
 				val &= ~(0x3ff<<22);
 				val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22);
-				val &= ~(1<<DqsRcvEnTrain);
+				val &= ~(1 << DqsRcvEnTrain);
 				Set_NB32(dev, reg, val);	/* program MaxRdLatency to correspond with current delay*/
 			}
 		}
@@ -497,7 +497,7 @@ static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat,
 	 * or normal ECC memory conditioning.
 	 */
 
-	//FIXME: this function depends on pDCTstat Array ( with Node id ) - Is this really a problem?
+	//FIXME: this function depends on pDCTstat Array (with Node id) - Is this really a problem?
 
 	u32 dev;
 	u8 Node;
@@ -592,9 +592,9 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
 					limit = pDCTstat->DCTSysLimit;
 				} else if (base == BottomIO) {
 					/* SW Node Hoist */
-					pMCTstat->GStatus |= 1<<GSB_SpIntRemapHole;
-					pDCTstat->Status |= 1<<SB_SWNodeHole;
-					pMCTstat->GStatus |= 1<<GSB_SoftHole;
+					pMCTstat->GStatus |= 1 << GSB_SpIntRemapHole;
+					pDCTstat->Status |= 1 << SB_SWNodeHole;
+					pMCTstat->GStatus |= 1 << GSB_SoftHole;
 					pMCTstat->HoleBase = base;
 					limit -= base;
 					base = _4GB_RJ8;
@@ -650,7 +650,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
 				val = Get_NB32(dev, reg);
 				Set_NB32(devx, reg, val);
 				reg += 4;
-			} while ( reg < 0x80);
+			} while (reg < 0x80);
 		} else {
 			break;			/* stop at first absent Node */
 		}
@@ -672,7 +672,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
 	u8 Node;
 	struct DCTStatStruc *pDCTstat;
 
-	if (!mctGet_NVbits(NV_DQSTrainCTL)){
+	if (!mctGet_NVbits(NV_DQSTrainCTL)) {
 		// FIXME: callback to wrapper: mctDoWarmResetMemClr_D
 	} else {	// NV_DQSTrainCTL == 1
 		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -723,7 +723,7 @@ static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat,
 	u8 Node;
 	struct DCTStatStruc *pDCTstat;
 
-	if (!mctGet_NVbits(NV_DQSTrainCTL)){
+	if (!mctGet_NVbits(NV_DQSTrainCTL)) {
 		// callback to wrapper: mctDoWarmResetMemClr_D
 	} else {	// NV_DQSTrainCTL == 1
 		for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -745,7 +745,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
 	u32 reg;
 
 	/* Ensure that a memory clear operation has completed on one node */
-	if (pDCTstat->DCTSysLimit){
+	if (pDCTstat->DCTSysLimit) {
 		reg = 0x110;
 
 		do {
@@ -834,7 +834,7 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
 		u32 reg_off = dct * 0x100;
 		val = 1<<DisDramInterface;
 		Set_NB32(pDCTstat->dev_dct, reg_off+0x94, val);
-		/*To maximize power savings when DisDramInterface=1b,
+		/*To maximize power savings when DisDramInterface = 1b,
 		  all of the MemClkDis bits should also be set.*/
 		val = 0xFF000000;
 		Set_NB32(pDCTstat->dev_dct, reg_off+0x88, val);
@@ -887,7 +887,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
 
 	dev = pDCTstat->dev_dct;
 	val = Get_NB32(dev, 0x94 + reg_off);
-	if (val & (1<<MemClkFreqVal)) {
+	if (val & (1 << MemClkFreqVal)) {
 		print_t("\t\t\tStartupDCT_D: MemClkFreqVal\n");
 		byte = mctGet_NVbits(NV_DQSTrainCTL);
 		if (byte == 1) {
@@ -997,7 +997,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 		pDCTstat->CASL = pDCTstat->DIMMCASL;
 
 		/* if "manual" memclock mode */
-		if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2)
+		if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 2)
 			pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1;
 
 	}
@@ -1013,10 +1013,10 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 	Trc = 0;
 	Twr = 0;
 	Twtr = 0;
-	for (i=0; i < 4; i++)
+	for (i = 0; i < 4; i++)
 		Trfc[i] = 0;
 
-	for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
+	for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
 		LDIMM = i >> 1;
 		if (pDCTstat->DIMMValid & (1 << i)) {
 			smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i);
@@ -1062,13 +1062,13 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 			if (Trc < val)
 				Trc = val;
 
-			/* dev density=rank size/#devs per rank */
+			/* dev density = rank size/#devs per rank */
 			byte = mctRead_SPD(smbaddr, SPD_BANKSZ);
 
 			val = ((byte >> 5) | (byte << 3)) & 0xFF;
 			val <<= 2;
 
-			byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE;     /* dev density=2^(rows+columns+banks) */
+			byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE;     /* dev density = 2^(rows+columns+banks) */
 			if (byte == 4) {
 				val >>= 4;
 			} else if (byte == 8) {
@@ -1094,7 +1094,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 	if (byte == 5)
 		DDR2_1066 = 1;
 	Tk40 = Get_40Tk_D(byte);
-	Tk10 = Tk40>>2;
+	Tk10 = Tk40 >> 2;
 
 	/* Notes:
 	 1. All secondary time values given in SPDs are in binary with units of ns.
@@ -1260,7 +1260,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 
 
 	/* Trfc0-Trfc3 */
-	for (i=0; i<4; i++)
+	for (i = 0; i < 4; i++)
 		pDCTstat->Trfc[i] = Trfc[i];
 
 	mctAdjustAutoCycTmg_D();
@@ -1277,7 +1277,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 	else
 		val -= Bias_TrcdT;
 
-	DramTimingLo |= val<<4;
+	DramTimingLo |= val << 4;
 
 	val = pDCTstat->Trp;
 	if (DDR2_1066)
@@ -1286,27 +1286,27 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 		val -= Bias_TrpT;
 		val <<= 1;
 	}
-	DramTimingLo |= val<<7;
+	DramTimingLo |= val << 7;
 
 	val = pDCTstat->Trtp;
 	val -= Bias_TrtpT;
-	DramTimingLo |= val<<11;
+	DramTimingLo |= val << 11;
 
 	val = pDCTstat->Tras;
 	if (DDR2_1066)
 		val -= Bias_TrasT_1066;
 	else
 		val -= Bias_TrasT;
-	DramTimingLo |= val<<12;
+	DramTimingLo |= val << 12;
 
 	val = pDCTstat->Trc;
 	val -= Bias_TrcT;
-	DramTimingLo |= val<<16;
+	DramTimingLo |= val << 16;
 
 	if (!DDR2_1066) {
 		val = pDCTstat->Twr;
 		val -= Bias_TwrT;
-		DramTimingLo |= val<<20;
+		DramTimingLo |= val << 20;
 	}
 
 	val = pDCTstat->Trrd;
@@ -1314,7 +1314,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 		val -= Bias_TrrdT_1066;
 	else
 		val -= Bias_TrrdT;
-	DramTimingLo |= val<<22;
+	DramTimingLo |= val << 22;
 
 
 	DramTimingHi = 0;	/* Dram Timing Low init */
@@ -1323,13 +1323,13 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
 		val -= Bias_TwtrT_1066;
 	else
 		val -= Bias_TwtrT;
-	DramTimingHi |= val<<8;
+	DramTimingHi |= val << 8;
 
 	val = 2;
-	DramTimingHi |= val<<16;
+	DramTimingHi |= val << 16;
 
 	val = 0;
-	for (i=4;i>0;i--) {
+	for (i = 4; i > 0; i--) {
 		val <<= 3;
 		val |= Trfc[i-1];
 	}
@@ -1385,7 +1385,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
 	proposedFreq = 533;	 /* Rev F0 programmable max memclock is */
 
 	/*Get User defined limit if  "limit" mode */
-	if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
+	if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
 		word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1);
 		if (word < proposedFreq)
 			proposedFreq = word;
@@ -1426,9 +1426,9 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
 
 	CL1min = 0xFF;
 	T1min = 0xFF;
-	for (k=K_MAX; k >= K_MIN; k--) {
+	for (k = K_MAX; k >= K_MIN; k--) {
 		for (j = J_MIN; j <= J_MAX; j++) {
-			if (Sys_Capability_D(pMCTstat, pDCTstat, j, k) ) {
+			if (Sys_Capability_D(pMCTstat, pDCTstat, j, k)) {
 				/* 1. check to see if DIMMi is populated.
 				   2. check if DIMMi supports CLj and Tjk */
 				for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) {
@@ -1480,7 +1480,7 @@ static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat,
 		mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 1);
 	}
 
-	if ( pDCTstat->_2Tmode == 2) {
+	if (pDCTstat->_2Tmode == 2) {
 		dev = pDCTstat->dev_dct;
 		reg = 0x94 + 0x100 * dct; /* Dram Configuration Hi */
 		val = Get_NB32(dev, reg);
@@ -1547,20 +1547,20 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
 		if (pDCTstat->Speed == 3) {
 			if (pDCTstat->MAdimms[dct] == 4)
 				DramConfigLo |= 1 << 5;		/* 50 Ohms ODT */
-		} else if (pDCTstat->Speed == 4){
+		} else if (pDCTstat->Speed == 4) {
 			if (pDCTstat->MAdimms[dct] != 1)
 				DramConfigLo |= 1 << 5;		/* 50 Ohms ODT */
 		}
 	} else {
 		// FIXME: Skip for Ax versions
 		if (pDCTstat->MAdimms[dct] == 4) {
-			if ( pDCTstat->DimmQRPresent != 0) {
+			if (pDCTstat->DimmQRPresent != 0) {
 				if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 4)) {
 					DramConfigLo |= 1 << 5;	/* 50 Ohms ODT */
 				}
 			} else if (pDCTstat->MAdimms[dct] == 4) {
 				if (pDCTstat->Speed == 4) {
-					if ( pDCTstat->DimmQRPresent != 0) {
+					if (pDCTstat->DimmQRPresent != 0) {
 						DramConfigLo |= 1 << 5;	/* 50 Ohms ODT */
 					}
 				}
@@ -1604,7 +1604,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
 
 	if (mctGet_NVbits(NV_ECC_CAP))
 		if (Status & (1 << SB_ECCDIMMs))
-			if ( mctGet_NVbits(NV_ECC))
+			if (mctGet_NVbits(NV_ECC))
 				DramConfigLo |= 1 << DimmEcEn;
 
 	DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct);
@@ -1633,7 +1633,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
 		DramConfigHi |= 1 << BankSwizzleMode; /* recommended setting (default) */
 
 	/* Check for Quadrank DIMM presence */
-	if ( pDCTstat->DimmQRPresent != 0) {
+	if (pDCTstat->DimmQRPresent != 0) {
 		byte = mctGet_NVbits(NV_4RANKType);
 		if (byte == 2)
 			DramConfigHi |= 1 << 17;	/* S4 (4-Rank SO-DIMMs) */
@@ -1641,7 +1641,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
 			DramConfigHi |= 1 << 18;	/* R4 (4-Rank Registered DIMMs) */
 	}
 
-	if (0) /* call back not needed mctOverrideDcqBypMax_D ) */
+	if (0) /* call back not needed mctOverrideDcqBypMax_D) */
 		val = mctGet_NVbits(NV_BYPMAX);
 	else
 		val = 0x0f; // recommended setting (default)
@@ -1676,14 +1676,14 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
 	 1. We will assume that MemClkDis field has been preset prior to this
 	    point.
 	 2. We will only set MemClkDis bits if a DIMM is NOT present AND if:
-	    NV_AllMemClks <>0 AND SB_DiagClks ==0 */
+	    NV_AllMemClks <>0 AND SB_DiagClks == 0 */
 
 
 	/* Dram Timing Low (owns Clock Enable bits) */
 	DramTimingLo = Get_NB32(dev, 0x88 + reg_off);
 	if (mctGet_NVbits(NV_AllMemClks) == 0) {
 		/* Special Jedec SPD diagnostic bit - "enable all clocks" */
-		if (!(pDCTstat->Status & (1<<SB_DiagClks))) {
+		if (!(pDCTstat->Status & (1 << SB_DiagClks))) {
 			const u8 *p;
 			byte = mctGet_NVbits(NV_PACK_TYPE);
 			if (byte == PT_L1)
@@ -1697,9 +1697,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
 			while (dword < MAX_DIMMS_SUPPORTED) {
 				val = p[dword];
 				print_tx("DramTimingLo: val=", val);
-				if (!(pDCTstat->DIMMValid & (1<<val)))
+				if (!(pDCTstat->DIMMValid & (1 << val)))
 					/*disable memclk*/
-					DramTimingLo |= 1<<(dword+24);
+					DramTimingLo |= 1 << (dword+24);
 				dword++ ;
 			}
 		}
@@ -1763,7 +1763,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
 		if ((pDCTstat->Status & (1 << SB_64MuxedMode)) && ChipSel >=4)
 			byte -= 3;
 
-		if (pDCTstat->DIMMValid & (1<<byte)) {
+		if (pDCTstat->DIMMValid & (1 << byte)) {
 			smbaddr = Get_DIMMAddress_D(pDCTstat, (ChipSel + dct));
 
 			byte = mctRead_SPD(smbaddr, SPD_ROWSZ);
@@ -1795,7 +1795,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
 			/* 13 Rows is smallest dev size */
 			byte |= Rows - 13;	/* CCCBRR internal encode */
 
-			for (dword=0; dword < 12; dword++) {
+			for (dword = 0; dword < 12; dword++) {
 				if (byte == Tab_BankAddr[dword])
 					break;
 			}
@@ -1803,14 +1803,14 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
 			if (dword < 12) {
 
 				/* bit no. of CS field in address mapping reg.*/
-				dword <<= (ChipSel<<1);
+				dword <<= (ChipSel << 1);
 				BankAddrReg |= dword;
 
 				/* Mask value=(2pow(rows+cols+banks+3)-1)>>8,
 				   or 2pow(rows+cols+banks-5)-1*/
 				csMask = 0;
 
-				byte = Rows + Cols;		/* cl=rows+cols*/
+				byte = Rows + Cols;		/* cl = rows+cols*/
 				if (Banks == 8)
 					byte -= 2;		/* 3 banks - 5 */
 				else
@@ -1824,19 +1824,19 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
 				csMask--;
 
 				/*set ChipSelect population indicator even bits*/
-				pDCTstat->CSPresent |= (1<<ChipSel);
+				pDCTstat->CSPresent |= (1 << ChipSel);
 				if (Ranks >= 2)
 					/*set ChipSelect population indicator odd bits*/
 					pDCTstat->CSPresent |= 1 << (ChipSel + 1);
 
-				reg = 0x60+(ChipSel<<1) + reg_off;	/*Dram CS Mask Register */
+				reg = 0x60+(ChipSel << 1) + reg_off;	/*Dram CS Mask Register */
 				val = csMask;
 				val &= 0x1FF83FE0;	/* Mask out reserved bits.*/
 				Set_NB32(dev, reg, val);
 			}
 		} else {
-			if (pDCTstat->DIMMSPDCSE & (1<<ChipSel))
-				pDCTstat->CSTestFail |= (1<<ChipSel);
+			if (pDCTstat->DIMMSPDCSE & (1 << ChipSel))
+				pDCTstat->CSTestFail |= (1 << ChipSel);
 		}	/* if DIMMValid*/
 	}	/* while ChipSel*/
 
@@ -1881,7 +1881,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
 
 	/* Check Symmetry of Channel A and Channel B DIMMs
 	  (must be matched for 128-bit mode).*/
-	for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) {
+	for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) {
 		if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) {
 			smbaddr = Get_DIMMAddress_D(pDCTstat, i);
 			smbaddr1 = Get_DIMMAddress_D(pDCTstat, i+1);
@@ -1889,35 +1889,35 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
 			byte = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0x1f;
 			byte1 = mctRead_SPD(smbaddr1, SPD_ROWSZ) & 0x1f;
 			if (byte != byte1) {
-				pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+				pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
 				break;
 			}
 
 			byte =	 mctRead_SPD(smbaddr, SPD_COLSZ) & 0x1f;
 			byte1 =	 mctRead_SPD(smbaddr1, SPD_COLSZ) & 0x1f;
 			if (byte != byte1) {
-				pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+				pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
 				break;
 			}
 
 			byte = mctRead_SPD(smbaddr, SPD_BANKSZ);
 			byte1 = mctRead_SPD(smbaddr1, SPD_BANKSZ);
 			if (byte != byte1) {
-				pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+				pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
 				break;
 			}
 
 			byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0x7f;
 			byte1 = mctRead_SPD(smbaddr1, SPD_DEVWIDTH) & 0x7f;
 			if (byte != byte1) {
-				pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+				pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
 				break;
 			}
 
 			byte = mctRead_SPD(smbaddr, SPD_DMBANKS) & 7;	 /* #ranks-1 */
 			byte1 = mctRead_SPD(smbaddr1, SPD_DMBANKS) & 7;	  /* #ranks-1 */
 			if (byte != byte1) {
-				pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+				pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
 				break;
 			}
 
@@ -1952,7 +1952,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
 
 	_DSpareEn = 0;
 
-	/* CS Sparing 1=enabled, 0=disabled */
+	/* CS Sparing 1 = enabled, 0 = disabled */
 	if (mctGet_NVbits(NV_CS_SpareCTL) & 1) {
 		if (MCT_DIMM_SPARE_NO_WARM) {
 			/* Do no warm-reset DIMM spare */
@@ -1967,7 +1967,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
 					pDCTstat->ErrStatus |= 1 << SB_SpareDis;
 			}
 		} else {
-			if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */
+			if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */
 				word = pDCTstat->CSPresent;
 				val = bsf(word);
 				word &= ~(1 << val);
@@ -1981,13 +1981,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
 	}
 
 	nxtcsBase = 0;		/* Next available cs base ADDR[39:8] */
-	for (p=0; p < MAX_DIMMS_SUPPORTED; p++) {
+	for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) {
 		BiggestBank = 0;
 		for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */
 			if (pDCTstat->CSPresent & (1 << q)) {  /* bank present? */
 				reg  = 0x40 + (q << 2) + reg_off;  /* Base[q] reg.*/
 				val = Get_NB32(dev, reg);
-				if (!(val & 3)) {	/* (CSEnable|Spare==1)bank is enabled already? */
+				if (!(val & 3)) {	/* (CSEnable|Spare == 1)bank is enabled already? */
 					reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/
 					val = Get_NB32(dev, reg);
 					val >>= 19;
@@ -2003,7 +2003,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
 			}	/*if bank present */
 		}	/* while q */
 		if (BiggestBank !=0) {
-			curcsBase = nxtcsBase;		/* curcsBase=nxtcsBase*/
+			curcsBase = nxtcsBase;		/* curcsBase = nxtcsBase*/
 			/* DRAM CS Base b Address Register offset */
 			reg = 0x40 + (b << 2) + reg_off;
 			if (_DSpareEn) {
@@ -2022,7 +2022,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
 		}
 
 		/* bank present but disabled?*/
-		if ( pDCTstat->CSTestFail & (1 << p)) {
+		if (pDCTstat->CSTestFail & (1 << p)) {
 			/* DRAM CS Base b Address Register offset */
 			reg = (p << 2) + 0x40 + reg_off;
 			val = 1 << TestFail;
@@ -2102,8 +2102,8 @@ static u8 Dimm_Supports_D(struct DCTStatStruc *pDCTstat,
 		byte = mctRead_SPD(DIMMi, word);	/* DIMMi speed */
 		if (Tk < byte) {
 			ret = 1;
-		} else if (byte == 0){
-			pDCTstat->ErrStatus |= 1<<SB_NoCycTime;
+		} else if (byte == 0) {
+			pDCTstat->ErrStatus |= 1 << SB_NoCycTime;
 			ret = 1;
 		} else {
 			ret = 0;	/* DIMM is capable! */
@@ -2121,12 +2121,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 	/* Check DIMMs present, verify checksum, flag SDRAM type,
 	 * build population indicator bitmaps, and preload bus loading
 	 * of DIMMs into DCTStatStruc.
-	 * MAAload=number of devices on the "A" bus.
-	 * MABload=number of devices on the "B" bus.
-	 * MAAdimms=number of DIMMs on the "A" bus slots.
-	 * MABdimms=number of DIMMs on the "B" bus slots.
-	 * DATAAload=number of ranks on the "A" bus slots.
-	 * DATABload=number of ranks on the "B" bus slots.
+	 * MAAload = number of devices on the "A" bus.
+	 * MABload = number of devices on the "B" bus.
+	 * MAAdimms = number of DIMMs on the "A" bus slots.
+	 * MABdimms = number of DIMMs on the "B" bus slots.
+	 * DATAAload = number of ranks on the "A" bus slots.
+	 * DATABload = number of ranks on the "B" bus slots.
 	 */
 
 	u16 i, j, k;
@@ -2159,7 +2159,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 			print_tx("\t DIMMPresence: smbaddr=", smbaddr);
 			if (smbaddr) {
 				Checksum = 0;
-				for (Index=0; Index < 64; Index++){
+				for (Index = 0; Index < 64; Index++) {
 					int status;
 					status = mctRead_SPD(smbaddr, Index);
 					if (status < 0)
@@ -2184,7 +2184,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 							pDCTstat->ErrCode = SC_StopError;
 						} else {
 							/*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/
-							pDCTstat->ErrStatus |= 1<<SB_DIMMChkSum;
+							pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum;
 							byte = mctRead_SPD(smbaddr, SPD_TYPE);
 							if (byte == JED_DDR2SDRAM)
 								pDCTstat->DIMMValid |= 1 << i;
@@ -2250,17 +2250,17 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 
 					/*Check if SPD diag bit 'analysis probe installed' is set */
 					byte = mctRead_SPD(smbaddr, SPD_ATTRIB);
-					if ( byte & JED_PROBEMSK )
-						pDCTstat->Status |= 1<<SB_DiagClks;
+					if (byte & JED_PROBEMSK)
+						pDCTstat->Status |= 1 << SB_DiagClks;
 
 					byte = mctRead_SPD(smbaddr, SPD_DMBANKS);
-					if (!(byte & (1<< SPDPLBit)))
+					if (!(byte & (1 << SPDPLBit)))
 						pDCTstat->DimmPlPresent |= 1 << i;
 					byte &= 7;
 					byte++;		 /* ranks */
 					if (byte > 2) {
 						/* if any DIMMs are QR, we have to make two passes through DIMMs*/
-						if ( pDCTstat->DimmQRPresent == 0) {
+						if (pDCTstat->DimmQRPresent == 0) {
 							MaxDimms <<= 1;
 						}
 						if (i < DimmSlots) {
@@ -2274,7 +2274,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 					if (devwidth == 16)
 						bytex = 4;
 					else if (devwidth == 4)
-						bytex=16;
+						bytex = 16;
 
 					if (byte == 2)
 						bytex <<= 1;	/*double Addr bus load value for dual rank DIMMs*/
@@ -2322,28 +2322,28 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 		if (RegDIMMPresent != 0) {
 			if ((RegDIMMPresent ^ pDCTstat->DIMMValid) !=0) {
 				/* module type DIMM mismatch (reg'ed, unbuffered) */
-				pDCTstat->ErrStatus |= 1<<SB_DimmMismatchM;
+				pDCTstat->ErrStatus |= 1 << SB_DimmMismatchM;
 				pDCTstat->ErrCode = SC_StopError;
 			} else{
 				/* all DIMMs are registered */
-				pDCTstat->Status |= 1<<SB_Registered;
+				pDCTstat->Status |= 1 << SB_Registered;
 			}
 		}
 		if (pDCTstat->DimmECCPresent != 0) {
-			if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid )== 0) {
+			if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) {
 				/* all DIMMs are ECC capable */
-				pDCTstat->Status |= 1<<SB_ECCDIMMs;
+				pDCTstat->Status |= 1 << SB_ECCDIMMs;
 			}
 		}
 		if (pDCTstat->DimmPARPresent != 0) {
 			if ((pDCTstat->DimmPARPresent ^ pDCTstat->DIMMValid) == 0) {
 				/*all DIMMs are Parity capable */
-				pDCTstat->Status |= 1<<SB_PARDIMMs;
+				pDCTstat->Status |= 1 << SB_PARDIMMs;
 			}
 		}
 	} else {
 		/* no DIMMs present or no DIMMs that qualified. */
-		pDCTstat->ErrStatus |= 1<<SB_NoDimms;
+		pDCTstat->ErrStatus |= 1 << SB_NoDimms;
 		pDCTstat->ErrCode = SC_StopError;
 	}
 
@@ -2418,7 +2418,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
 	} else {
 		/* Configure DCT1 if unganged and enabled*/
 		if (!pDCTstat->GangedMode) {
-			if ( pDCTstat->DIMMValidDCT[1] > 0) {
+			if (pDCTstat->DIMMValidDCT[1] > 0) {
 				print_t("\tmct_initDCT: DCTInit_D 1\n");
 				err_code = pDCTstat->ErrCode;		/* save DCT0 errors */
 				pDCTstat->ErrCode = 0;
@@ -2497,7 +2497,7 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
 	if (byte != bytex) {
 		pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO);
 	} else {
-		if ( mctGet_NVbits(NV_Unganged) )
+		if (mctGet_NVbits(NV_Unganged))
 			pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
 
 		if (!(pDCTstat->ErrStatus & (1 << SB_DimmMismatchO))) {
@@ -2595,7 +2595,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
 		i_start = dct;
 		i_end = dct + 1;
 	}
-	for (i=i_start; i<i_end; i++) {
+	for (i = i_start; i < i_end; i++) {
 		index_reg = 0x98 + (i * 0x100);
 		Set_NB32_index_wait(dev, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A Output Driver Compensation Control */
 		Set_NB32_index_wait(dev, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A Output Driver Compensation Control */
@@ -2615,7 +2615,7 @@ static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat)
 		print_tx("mct_SyncDCTsReady: Node ", pDCTstat->Node_ID);
 		dev = pDCTstat->dev_dct;
 
-		if ((pDCTstat->DIMMValidDCT[0] ) || (pDCTstat->DIMMValidDCT[1])) {		/* This Node has dram */
+		if ((pDCTstat->DIMMValidDCT[0]) || (pDCTstat->DIMMValidDCT[1])) {		/* This Node has dram */
 			do {
 				val = Get_NB32(dev, 0x110);
 			} while (!(val & (1 << DramEnabled)));
@@ -2629,7 +2629,7 @@ static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u8 dct)
 {
 	if (!pDCTstat->GangedMode) {
-		if (dct == 0 ) {
+		if (dct == 0) {
 			pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct];
 			if (pDCTstat->DIMMValidDCT[dct] == 0)
 				pDCTstat->ErrCode = SC_StopError;
@@ -2648,7 +2648,7 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,
 {
 	u8 ret;
 
-	if ( dct == 0) {
+	if (dct == 0) {
 		SPDCalcWidth_D(pMCTstat, pDCTstat);
 		ret = mct_setMode(pMCTstat, pDCTstat);
 	} else {
@@ -2752,7 +2752,7 @@ static u8 mct_DIMMPresence(struct MCTStatStruc *pMCTstat,
 {
 	u8 ret;
 
-	if ( dct == 0)
+	if (dct == 0)
 		ret = DIMMPresence_D(pMCTstat, pDCTstat);
 	else
 		ret = pDCTstat->ErrCode;
@@ -2777,7 +2777,7 @@ static void mct_OtherTiming(struct MCTStatStruc *pMCTstat,
 				pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0];
 				Set_OtherTiming(pMCTstat, pDCTstat, 0);
 			}
-			if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode ) {
+			if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) {
 				pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1];
 				Set_OtherTiming(pMCTstat, pDCTstat, 1);
 			}
@@ -3022,8 +3022,8 @@ static u8 Check_DqsRcvEn_Diff(struct DCTStatStruc *pDCTstat,
 	if (index == 0x12)
 		ecc_reg = 1;
 
-	for (i=0; i < 8; i+=2) {
-		if ( pDCTstat->DIMMValid & (1 << i)) {
+	for (i = 0; i < 8; i+=2) {
+		if (pDCTstat->DIMMValid & (1 << i)) {
 			val = Get_NB32_index_wait(dev, index_reg, index);
 			byte = val & 0xFF;
 			if (byte < Smallest_0)
@@ -3153,8 +3153,8 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat,
 	if (index == 0x12)
 		ecc_reg = 1;
 
-	for (i=0; i < 8; i+=2) {
-		if ( pDCTstat->DIMMValid & (1 << i)) {
+	for (i = 0; i < 8; i+=2) {
+		if (pDCTstat->DIMMValid & (1 << i)) {
 			val = Get_NB32_index_wait(dev, index_reg, index);
 			val &= 0x00E000E0;
 			byte = (val >> 5) & 0xFF;
@@ -3192,11 +3192,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
 
 	Smallest = 3;
 	Largest = 0;
-	for (i=0; i < 2; i++) {
+	for (i = 0; i < 2; i++) {
 		val = Get_NB32_index_wait(dev, index_reg, index);
 		val &= 0x60606060;
 		val >>= 5;
-		for (j=0; j < 4; j++) {
+		for (j = 0; j < 4; j++) {
 			byte = val & 0xFF;
 			if (byte < Smallest)
 				Smallest = byte;
@@ -3308,14 +3308,14 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
 
 	/* Copy dram map from F1x40/44,F1x48/4c,
 	   to F1x120/124(Node0),F1x120/124(Node1),...*/
-	for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) {
+	for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
 		pDCTstat = pDCTstatA + Node;
 		devx = pDCTstat->dev_map;
 
 		/* get base/limit from Node0 */
 		reg = 0x40 + (Node << 3);		/* Node0/Dram Base 0 */
 		val = Get_NB32(dev, reg);
-		Drambase = val >> ( 16 + 3);
+		Drambase = val >> (16 + 3);
 
 		reg = 0x44 + (Node << 3);		/* Node0/Dram Base 0 */
 		val = Get_NB32(dev, reg);
@@ -3335,7 +3335,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
 			val |= Dramlimit;
 			Set_NB32(devx, reg, val);
 
-			if ( pMCTstat->GStatus & ( 1 << GSB_HWHole)) {
+			if (pMCTstat->GStatus & (1 << GSB_HWHole)) {
 				reg = 0xF0;
 				val = Get_NB32(devx, reg);
 				val |= (1 << DramMemHoistValid);
@@ -3476,7 +3476,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
 
 	val = Get_NB32_index_wait(dev, index_reg, 0x00);
 	dword = 0;
-	for (i=0; i < 6; i++) {
+	for (i = 0; i < 6; i++) {
 		switch (i) {
 			case 0:
 			case 4:
@@ -3652,8 +3652,8 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
 	u32 dev = pDCTstat->dev_dct;
 
 	// FIXME: skip for Ax
-	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
-		for (i=0; i < 2; i++) {
+	if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
+		for (i = 0; i < 2; i++) {
 			reg_off = 0x100 * i;
 			Set_NB32(dev,  0x98 + reg_off, 0x0D000030);
 			Set_NB32(dev,  0x9C + reg_off, 0x00000806);
@@ -3667,7 +3667,7 @@ static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
 			struct DCTStatStruc *pDCTstat, u8 *dqs_pos)
 {
 	// FIXME: Skip for Ax
-	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
+	if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
 		*dqs_pos = 32;
 	}
 }
@@ -3737,7 +3737,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat,
 	msr = BU_CFG2;
 	_RDMSR(msr, &lo, &hi);
 	if (!pDCTstat->ClToNB_flag)
-		lo &= ~(1<<ClLinesToNbDis);
+		lo &= ~(1 << ClLinesToNbDis);
 	_WRMSR(msr, lo, hi);
 
 }
@@ -3783,10 +3783,10 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
 	 * Solution: From the bug report:
 	 *  1. A software-initiated frequency change should be wrapped into the
 	 *     following sequence :
-	 * 	- a) Disable Compensation (F2[1, 0]9C_x08[30] )
+	 * 	- a) Disable Compensation (F2[1, 0]9C_x08[30])
 	 * 	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
 	 * 	c) Do frequency change
-	 * 	d) Enable Compensation (F2[1, 0]9C_x08[30] )
+	 * 	d) Enable Compensation (F2[1, 0]9C_x08[30])
 	 *  2. A software-initiated Disable Compensation should always be
 	 *     followed by step b) of the above steps.
 	 * Silicon Status: Fixed In Rev B0
@@ -3970,7 +3970,7 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
 	if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) {
 		mct_Wait(10000);	/* Wait 50 us*/
 		val = Get_NB32(dev, 0x110);
-		if ( val & (1 << DramEnabled)) {
+		if (val & (1 << DramEnabled)) {
 			/* If 50 us expires while DramEnable =0 then do the following */
 			val = Get_NB32(dev, 0x90 + reg_off);
 			val &= ~(1 << Width128);		/* Program Width128 = 0 */
@@ -3990,9 +3990,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
 
 /* ==========================================================
  *  6-bit Bank Addressing Table
- *  RR=rows-13 binary
- *  B=Banks-2 binary
- *  CCC=Columns-9 binary
+ *  RR = rows-13 binary
+ *  B = Banks-2 binary
+ *  CCC = Columns-9 binary
  * ==========================================================
  *  DCT	CCCBRR	Rows	Banks	Columns	64-bit CS Size
  *  Encoding