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path: root/src/northbridge/amd/amdmct/mct/mct_d.c
AgeCommit message (Expand)Author
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
2018-10-30{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macrosElyes HAOUAS
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
2017-01-12amd/mct/ddr2: Remove orphaned Tab_TrefT_k variableTimothy Pearson
2017-01-10amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStrucTimothy Pearson
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
2016-11-09nb/amd/amdmct/mct: Remove commented codeElyes HAOUAS
2016-10-04src/northbridge: Remove unnecessary whitespaceElyes HAOUAS
2016-09-21northbridge/amd/amdmct: Improve code formattingElyes HAOUAS
2016-08-31northbridge/amd: Add required space before opening parenthesis '('Elyes HAOUAS
2016-08-23src/northbridge: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
2015-11-14northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tablesTimothy Pearson
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-26northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalizationTimothy Pearson
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-04-01northbridge/amd/amdfam10: Collect DIMM information for ramstage useTimothy Pearson
2015-03-07northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and laterTimothy Pearson
2015-01-06northbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
2014-05-23northbridge/amd/amdmct: Superfluous parenthesis in if-statementsEdward O'Callaghan
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2012-03-02Fix ECC disable option for AMD Fam10 DDR2 and DDR3.Marc Jones
2011-03-28Add AMD C32 support.Zheng Bao
2011-01-06Fix some settings fo AMD MCT. It is based on BIOS test suite.Zheng Bao
2010-10-08Trivial. Spell checking.Zheng Bao
2010-09-28Trivial. re-Indent the code.Zheng Bao
2010-09-27Obviously missing brackets.Xavi Drudis Ferran
2010-09-21Complete the code which was missing.Zheng Bao
2010-09-09Please find appended. This patch gets rid of the %gs magic altogether,Arne Georg Gleditsch
2010-09-09Also improve boot time on AMD for the DDR3 code path.Arne Georg Gleditsch
2010-09-09Apparently, it's not crucial to clear this at the exact moment we switchArne Georg Gleditsch
2010-09-04AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.Kerry She
2010-04-30Get rid of a few more warnings.Myles Watson
2010-04-27Since some people disapprove of white space cleanups mixed in regular commitsStefan Reinauer
2010-04-16zero warnings days: unify mp tables. fix warnings.Stefan Reinauer
2010-04-15Remove a few more warnings from fam10.Myles Watson
2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
2009-09-14Use the coreboot pci config read/write functions instead of direct cf8/cfcMarc Jones
2009-08-25Without this patch, if we only got a DIMM in Channel B, memory can not beZheng Bao
2009-06-06Fix for Erratum 350 for AMD Fam10h CPUs.Marco Schmidt
2008-12-05Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>Stefan Reinauer
2008-07-23Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).Marc Jones
2008-04-11Bring Fam10 memory controller init up to date with the latest AMD BKDGMarc Jones (marc.jones
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
2007-12-19Initial AMD Barcelona support for rev Bx.Marc Jones