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Update PL1 Min value from 6W to 15W based on the brox thermal cooling
capacity and hardware design.
BUG=None
BRANCH=None
TEST=Build and boot on brox board
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When world-facing camera is absent, coreboot need to enable
GPP_R6(DMIC_WCAM_CLK) and GPP_R7(DMIC_WCAM_DATA) for 3rd dmic support
BUG=b:333973512
TEST=Boot google/riven to OS and verify 3rd dmic working properly.
Change-Id: I6c8780ce37b5d3987f5cdf6e6e6d0b4896b33230
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84141
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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With `probe unprovisioned` fw_config rule, there is no need to define an
explicit STORAGE_UNKNOWN option. Hence remove it.
BUG=None
TEST=Build Jubilant FW image.
Change-Id: I4f6ace4b39a1ee0b63486d3872b20c8da719ae4a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84095
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tune I2C2 timing:
Set falling time to 250ns from 400ns to meet spec: "THIGH>0.6us"
BUG=b:362685374
TEST= Build jubilant firmware
Measure the i2c signal on jubilant to meet spec:
I2C2 THIGH from 0.494 us to 0.76 us
Change-Id: I42a60edc0b361bfabacf5376ef89f436efedb356
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84143
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: I41a877ed7f5f3d02904dc939b32996a7f6d45373
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Generate RAM IDs of lp5 memory:
1)Hyinx 4GB*4 H58G56BK8BX068
2)SAMSUNG 4GB*4 K3KL8L80CM-MGCT
BUG=None
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I6b6e351ceaacfd65eae7b1db14c195b34359689a
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
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Modify the FP IRQ pin to GPP_D13 from GPP_F15 from HW change on EVT.
The design change to follow the brox's GPE0 routing, and the
FP wake source can be routed.
BUG=b:363166664
TEST= Build jubilant firmware
Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84124
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial support for the LattePanda Mu board, which features:
- Intel Alder Lake-N N100 processor
- Samsung K3LK7K70BM-BGCP, 8GB LPDDR5 memory
- Samsung KLMCG2UCTA-B041, 64GB eMMC storage
- SO-DIMM 260-pin connector for function expansion
This commit includes:
- Basic board configuration
- Memory initialization
- Essential I/O setup
- Used UEFITool NE alpha 68 (Nov 4 2023) to extract data.vbt file
from original BIOS
- BIOS download link: https://github.com/LattePandaTeam/LattePanda-Mu
located at "./Softwares/BIOS/DFLT/LP-BS-S70NC1R200-SR-A.bin.zip"
Test Environment:
- Carrier Board: Lite
- Payload: mrchromebox/edk2
- EDK2 Version: uefipayload_202309
Test result
Passed:
- Windows 11 boot from eMMC
- Install Ubuntu 24.04 on NVMe SSD
- Ubuntu 24.04 boot from NVMe SSD
- USB 3.0/2.0 functionality
- Realtek RTL8111H-CG-RH Ethernet
- HDMI Display
- Audio over HDMI work in Ubuntu 24.04
Known Issues:
- S3 sleep mode non-functional
- Power-on after shutdown requires power removal
- SuperIO UART not detected in Windows 11
- Audio over HDMI not work in Windows 11
- Windows 11 BSOD occurs with NVMe SSD installed:
- Stop code: Machine Check Exception
- NVMe SSD not working on Windows 11, except when:
- KDNet Debugging enabled on NIC during boot
- SSD becomes functional in this scenario
Change-Id: I79696bdd837a221860b32f54629212c3346dca66
Signed-off-by: KunYi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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De-assert PERST# at romstage to reduce the waiting time in ramstage.
Before
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
After
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST#
[DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries)
```
BUG=none
TEST=boot from NVMe
Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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On the non-vboot boot path, eSPI is configured as part of
fch_pre_init(), and we need to ensure that the mainboard sets the
eSPI GPIOs properly before the common SoC code performs eSPI init.
Use the mb_set_up_early_espi() function to set the eSPI GPIOs at
the correct time.
TEST=build/boot google/zork (morphius), verify keyboard functional.
Change-Id: I03efe6def37a018c3de410523be21bf008174e94
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84148
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that zork can boot without vboot, ensure that the GPIOs set in
verstage are programmed in bootblock on the non-vboot path.
The eSPI GPIOs will be set in a subsequent patch using
mb_set_up_early_espi() since setting them in
bootblock_mainboard_early_init() would be too late given when the
SoC eSPI init takes place.
TEST=build/boot google/zork (morphius) w/o vboot
Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add a new fw config field for wifi category as WIFI_6_8852, which is
PCIe based. Also, enable WIFI_6_8852 for existing PCIe based wifi port
as well as bluetooth port.
BUG=b:356434907
BRANCH=NONE
TEST=Verified Wifi6 module detection
Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84138
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login
screen, it is because it inserts 12 blank frames if it receives the
unmute in VB-ID.
Always override the mute in VB-ID to avoid Tcon EC detected the
audiomute_flag change.
BUG=b:360243615
BRANCH=firmware-nissa-15217.B
TEST:Verfied on Teliks and cannot reproduce the issue
Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84137
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
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Bluetooth driver in kernel requires reset-gpio in current resource
settings (_CRS) and device specific data (_DSD) ACPI objects. Hence
remove ACPI Power Resource for Bluetooth device so that the concerned
ACPI objects get populated.
BUG=b:362817900
TEST=Build Brox Firmware image and boot to OS. Ensure that the _CRS and
_DSP ACPI objects are filled in the SSDT with the required data.
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x004D
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"reset-gpio",
Package (0x04)
{
\_SB.PCI0.XHCI.RHUB.HS10,
Zero,
Zero,
One
}
}
}
})
Change-Id: If6e679aa3f4181e7963ac53d0847b1512959b3a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84135
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update dptf settings from thermal design:
1) Remove fan control and active policy,
since fan is controlled by EC.
2) Modify TSRs to 0:DRAM, 1:SOC, 2:Charger
3) Update Pl2 min&max values
BUG=None
TEST= Build jubilant firmware
Generate and check ACPI SSDT.dsl
$ cat /sys/firmware/acpi/tables/SSDT > SSDT
$ iasl -d SSDT
Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
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The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on
the mainboard and likely also routes one USB2 port to the m.2 E key slot
which is typically used for Bluetooth support when an E key m.2 WIFI +
Bluetooth card is installed.
This is untested, since I only have the cw-al-4l-v2.0 mainboard, but
from looking at the documentation of the version 1 and looking at how
things are done on the version 2 this should be correct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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1) Add all required changes for eSOL support.
2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo.
The CSOT (MNC207QS1-1) panel is used for the devicetree.
BUG=b:362895813
TEST=On-screen text message seen during MRC training on Trulo SKU1.
MRC: no data in 'RW_MRC_CACHE'
bootmode is set to: 0
DP PHY mode status not complete
DP PHY mode status not complete
DP PHY mode status not complete
...
Informing user on-display of memory training
Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
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Update verb table provided by Realtek on 20240710.
Restults: SNR > 90 (spec>=90).
BUG=b:349996984
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: Ic4f03d09010efa7e32713b2697d5832255f64317
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83920
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: Id0ab5e641684e03da555a127808c0def5a53cbe6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84156
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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By default, QEMU bails when trying to use bigger images mounted with
'-drive if=pflash', which is required to make use of writable flash
introduced in CB:82555. This changes both default size in Kconfig as
well as FMAP layouts.
Since QEMU 5.0.0 it is possible to change the limit of firmware size
with `max-fw-size` machine configuration option, up to 16 MiB, as bigger
sizes would overlap with IO APIC memory range. Default is still 8 MiB,
so it makes sense to have identical default in coreboot.
Error thrown by QEMU when trying to use too big ROM:
qemu-system-x86_64: combined size of system firmware exceeds 8388608 bytes
Change-Id: If36cb754a8e75e23bce49ff568dd88e5db279bb8
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82639
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating
Intel chipset. In addition, even though it implements SMI_STS register,
QEMU never sets any bits in it. As there is little emulated hardware
that can be generating SMI, assume that all SMIs come from APM. This
source is used e.g. to disable ACPI (which wasn't working until now on
QEMU) and SMMSTORE.
Tested by invoking SMMSTORE commands from the payload with SMM logging.
Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82558
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We have to reset the USB hub as early as possible. Otherwise the USB3
hub may not be usable in the payload. This design has been introduced
since Cherry.
TEST=build pass.
BUG=b:317009620
Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84024
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add usb host function support.
TEST=read usb data successfully.
BUG=b:317009620
Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com>
Change-Id: I5d081ff3e7367b87fab5ebdcb148c9005ab583f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL).
BUG=b:358439747
TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C.
Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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With `probe unprovisioned` fw_config rule, there is no need to define an
explicit STORAGE_UNKNOWN option. Hence remove it.
BUG=None
TEST=Build Lotso FW image.
Change-Id: Ia170a6e006cb51e95fbaf3efe1106ca907165eca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84094
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This feature is not required in Brox devices. Hence disable the
concerned device.
BUG=None
TEST=Build Brox firmware and boot to OS. Ensure that the concerned
device is disabled in the OS.
Change-Id: I355852c780c552e6f9b2c28508f53580f392c1b9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84093
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
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`boot_dev` can be const, and we can use MEM_REGION_DEV_INIT() as all
the values are known at compile time.
Change-Id: Icd3757ba4b5e8bfbee9e9c9d18bf0ee71520a8ac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84089
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login
screen, it is because it inserts 12 blank frames if it receives the
unmute in VB-ID.
Always override the mute in VB-ID to avoid Tcon EC detected the
audiomute_flag change.
BUG:b=357764688
BRANCH=firmware-nissa-15217.B
TEST:Verfied on Anraggar and cannot reproduce the issue
Change-Id: I711dfd0803440e4b04f02849fed529c3872e023d
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
TEST=Build and boot nivviks. Monitor the camera LED blinking
during boot.
Change-Id: I979207d1b6d55f78dea20d3366ef4a833ee9c86d
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
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This patch removes the HAVE_ACPI_RESUME config option from the Google
Rex mainboard configuration. The Intel Meteor Lake SoC does not support
S3 (ACPI sleep state) entry/exit, and attempting S3 validation could
lead to abnormal platform behavior. This change ensures that `_S3` is
not listed as a valid wake source in the DSDT (Differentiated System
Description Table) after booting to the OS.
BUG=b:351025543
TEST=Booted google/rex successfully and verified that the `_S3` name
variable is not present in the DSDT.
Change-Id: I730ade628eea84c60ba003a0c871e729b0ee0a9f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84081
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This was adapted from CB:22693 from Iru Cai, which was based on
autoport. I do not physically have this system. Someone with physical
access to an E6230 running version A11 of the vendor firmware sent me
the VBT after running the command `intelvbttool --inlegacy --outvbt
data.vbt`. This new version of the port has not yet been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Original-Change-Id: I8cdc01e902e670310628809416290045c2102340
Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82153
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboard is QAL70/LA-7741P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A21 of the vendor firmware. This port has not been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I827826e9ff8a9a534c50250458b399104478e06c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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|
Mainboard is codenamed Vida. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. The VBT was obtained using
intelvbttool while running version A14 (latest available version) of the
vendor firmware.
Tested and found to boot as part of a libreboot build based on upstream
coreboot commit b7341da191 with additional patches, though these do not
appear to affect SNB/IVB. The base E6430 patch was tested against
coreboot main.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82131
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Mainboard is PAL70/LA-6611P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A22 of the vendor firmware. This port has not been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82130
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Mainboard is Krug 14". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then
modified to produce this port. I was also sent the VBT binary, which was
obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
A02 of the vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I0283653156083768e1fd451bcf539b4e028589f4
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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|
Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port. I was also sent the VBT binary, which was obtained
from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the
vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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|
Based on autoport. data.vbt extracted from a running system
using "intelvbttool --inlegacy"
Like with 8200 SFF, OEM firmware write-protects itself, but not
the IFD, GBE or ME regions when FDO jumper is applied. Therefore,
ME can be shrunken with me_cleaner and BIOS region moved there.
Tested:
- Internal flashing from the latest endor BIOS (v2.33)
- Sandy Bridge Pentium G630 CPU
- RAM: 8+0, 8+4, 8+8 1866MHz DDR3
- SeaBIOS 1.16.2, metest86+ v6, coreinfo, nvramcui & tint payloads
- libgfxinit txtmode & corebootfb
- VGA, DisplayPort (DVI monitor through an adapter)
- Gigabit Ethernet
- All front and back USB ports
- Booting Void Linux
- Rebooting
- Mini-PCIe WLAN (PCIe)
- Both SATA ports: 2.5" & DVD
- PS/2 keyboard and mouse
- Fan control
- TPM settings in SeaBIOS
Untested:
- Second Mini-PCIe slot (or is it mSATA): connector not present on my unit
- MXM graphics
Not working:
S3: it sleeps for a few seconds and wakes up on its own
Change-Id: I1cba7a5e664758eba7ea2ab8a55658b307d1d173
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79583
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested to still boot, SeaBIOS -> Void Linux
Change-Id: I03d57c7e76ccdfccd58b2a6deab4dee87b02503a
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79545
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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|
Mainboard is Krug 15". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then
modified to produce this port. I was also sent the VBT binary, which was
obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
A14 of the vendor firmware.
This was originally tested and found to be working as a standalone
board port in Libreboot, but this variant based port in upstream
coreboot has not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port. I was also sent the VBT binary, which was obtained
from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the
vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82126
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A21 of the vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port.
I was also sent the vbios obtained using intel_bios_dumper while running
version A22 of the vendor firmware, which I then processed using
`intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt.
This was originally tested and found to be working as a standalone board
port in Libreboot, though this variant based port in upstream coreboot
has not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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|
Introduce a sandybridge-style devicetree setting for SPD addresses,
and use it instead of runtime code in mb_get_spd_map() for all
haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all
boards except google/slippy.
Patch also covers recently added Z97 boards using Broadwell MRC.
Also update util/autoport to match.
abuild passes for all affected boards.
autoport builds, but otherwise untested.
Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Change-Id: Ia3fda208f5cb2e0d8a1e4da2c4392bc0f326d1ed
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84076
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit aa6865291a7ddfae4c67fcfc55ebd0c13a376807.
Reason for revert: We applied this patch for touchpad stuttering issue
for XOl, but the same touchpad problem was reported. So we would revert
this change and apply kernel patch (crrev/c/5808335) to avoid the
touchpad issue.
Change-Id: I78139932e76dbd4128fb325dd70b7dcff3bcc81c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Initialize SPI NOR Flash Controller (SNFC) in the bootblock.
TEST=read nor flash data successfully.
BUG=b:317009620
Change-Id: I88960ce7a50f67ea6f402884b714cb205836a6d8
Signed-off-by: Noah Shen <noah.shen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83924
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the weak function. Combine all the getting descriptors together.
BUG=b:279144932
TEST=Build
Change-Id: I981e9c52c8e5fa32296e2e43be47411557133691
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83646
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: Ic0e0864b99c5078e5b84b9183262b3c47ffcb329
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG
for WIFI_CATEGORY to choose the right wifi_sar hex file.
Below is the file mapping:
wifi_sar_0.hex = wifi6
wifi_sar_1.hex = wifi7
BUG=b:345596420
TEST=emerge-nissa coreboot chromeos-bootimage
Cq-Depend: chrome-internal:7607427
Change-Id: If8339a2a1d32d3e885ef87ea2ec2847f107f1fbd
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84051
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify DPTF parameters from thermal team.
1. Add TCHG.
2. Modify the charging limit.
BUG=b:360066326
TEST=Modify Thermal according to design requirements
Change-Id: Ia7050b552656a70da0c992e4f54b02ccb6a7c114
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83929
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar
|
|
Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:348258637
TEST=Local build successfully and boot to OS normally.
Change-Id: I59c420c03a8f01d185f616a2212798266b4251e0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
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EE change GPP_C1 from pull-up to OD&no pull-up in PCH GPIO Table.
BUG=b:358472598
TEST=Build and verified test result by EE team
Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83904
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: I0908ff500434401bf89a5313427cf304f32cf929
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
|
|
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: Ie8174567b863e1afe8b0a27e644e24e9d3de6d19
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84020
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Add the condition of unprovisioned fw_config to enable all storages
and devices. It's for first boot on all storags and preliminary test
in factory when fw_config is unprovisioned.
BUG=None
TEST=Build jubilant firmware and boot to OS on storages when fw_config
is unprovisioned and ensure all devices are enable.
Change-Id: Ia14632744c34548e2c201dfc58d82515cdd02df0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84002
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Storage devices are very critical to boot to OS. When probe list is
defined for storage devices, all of them get disabled when fw_config is
unprovisioned - a typical situation in the factory. Fix this by
configuring the storage devices in device/override tree to probe and
enable them when fw_config is unprovisioned.
BUG=None
TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned.
Change-Id: I0537f7d1d83293b9b3408f0aadf11fa2e7908163
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83984
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the voltage value measured by the USB2 pin of the wlan is 500mv,
it does not meet the design requirements. Adjusting the port length
can reduce the voltage to 450mv, which meets the expected settings.
BUG=b:361037189
TEST=1. The voltage measurements are as expected.
2. The Bluetooth and WiFi functions of the wlan module are
verified to be normal.
Change-Id: Icd1ec3b561ee5b3f55e5f97a56fd9cb7df893508
Signed-off-by: zengqinghong <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Enables early serial console for debugging.
TEST=build/boot drobit, verify console output available starting in
bootblock on CPU UART (/dev/ttyUSB1) vs ramstage.
Change-Id: If94eb8caca3469143433fef06b972050f886be6a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This mainboard does not have AT24RF08C (Asset Identification EEPROM) and
will show "*INVALID*" in the SMBIOS table.
Change-Id: If6f948bc4c63c7afdc8b31e1945d3c3beb99883f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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|
Change-Id: Icc5546a8073c03ce77480b634b367d10d1ad0111
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83992
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: Iaa761108acbf275820ecbec9837b81bc5d64613e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83991
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Enable Intel CrashLog diagnostic feature by default on all Google
Dedede variants.
BUG=b:354834461
TEST=Built for Google Dedede and verifed that CrashLog is enabled by
default.
Change-Id: Ib0487bd6a5bfdad2a80fd0787e009e48f4527d38
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Kinox has two VBT options, selected via fw_config. Add the second
option to CBFS, and update the original file.
Extracted from Google_Kinox.14505.704.0.bin.
TEST=build/boot kinix, verify firmware display init successful and
payload menu visible. Verify correct VBT selected via cbmem log.
Change-Id: I01c19222628fee3874ef592ec40b40d9bd679dce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83996
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested to still boot, SeaBIOS -> Void Linux
Change-Id: Idc61e5d17f4c71fc50cf87c60a5063fc893c1d8c
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79544
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify brox DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.
Change-Id: I5cd36640677996209beb8fe29f522ff8e07ebf00
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=None
TEST=verify rex DUT is able to power down and stay powered down when
selecting the "Power off" button in the firmware dev screen.
Change-Id: I3fdc02a82d197fd2b075e0a66c578149cef3a69f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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|
The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source. This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.
BUG=b:360380950, b:359692570
BRANCH=firmware-brya-14505.B
TEST=verify brask, nissa, or brya DUT is able to power down and stay
powered down when selecting the "Power off" button in the firmware dev
screen.
Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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With commit 26b1a5f62b ("mb/acer/g43t-am3: Rework mainboard for variant
mechanism"), the files related to the G43T-AM3 mainboard were supposed
to be moved into its own variant directory. However, it seems it was
forgotten to delete the old ones and thus remove the duplicates.
Change-Id: I450fab074621d21e80216e4667eaf2510b0e14ad
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83985
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the ITE mirror functionality; all devices will mirror
automatically when they exit G3, and this is good enough.
Change-Id: I9b82e1b1386b4607dfe7da9b25ba432ec0303cf8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83629
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously RAM probing was necessary for our QEMU-RISCV target in order
to find the available amount of memory.
Now we get the memory from the devicetree propagated by QEMU, so there
is no reason to keep it anymore.
Tested:
Start QEMU-RISCV and cause an exception to make sure the trap handler
still works.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9b1e0dc78fc2a66d6085fe99a71245ff46f8e63c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83873
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adjust settings as recommended by thermal team.
Set tcc_offset value to 12 in devicetree.
BUG=b:308704811
BRANCH=firmware-rex-15709.B
TEST=emerge-ovis coreboot chromeos-bootimage
built bootleg and verified test result by thermal team
Change-Id: I0ae97bb0b2dbb2fe8f35221522506ec1f7da47f6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83971
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: I87cfbdd0b8a97d84a96af373855219c60f39f173
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: Ib654f22033c68edbc602f14537aaa2151800598d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83943
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change STORAGE_UNPROVISIONED to STORAGE_UNKNOWN depend on depthcharge setting.
BUG=None
TEST=emerge-brox coreboot
Set STORAGE_UNKNOWN on jubilant, check that NVMe and UFS can boot.
Change-Id: I4cfd7322c2940862dfbae46e85522715cd7534c1
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83935
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
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Before:
I2C2 - 431KHz
I2C4 - 413KHz
After:
I2C2 - 364KHz
I2C4 - 370KHz
BUG=b:351968527
TEST=Rate of the actual measured machine is pass.
Change-Id: Ieb75db1dc95ffd5ca806a194ae678c700fa0741c
Signed-off-by: Wei Hualin <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83906
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Set up soundbar-related GPIOs for updating.
BUG=b:358435383
TEST=emerge-constitution coreboot chromeos-bootimage
Change-Id: I517da8de90487533e49e46649c5acf4ccfcc5160
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes WWAN configuration from the bootblock.
It appears that setting it up in the bootblock may not be necessary.
Configure in bootblock,the seq will be triggered at the same time.
The customer would like us to leave some buffer for EN to RST.
BUG=b:357764679
TEST=Build and verified test result by EE team
Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83792
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds a new board as a variant of the Acer G43T-AM3 with the
following prominent changes:
* Intel Q45 northbridge (GMCH) instead of a G43
* 4 MiB of flash instead of 2 MiB
* Two serial ports (one external, one internal)
* A parallel port connector (internal)
* An FDD connector
* DVI-D instead of HDMI
* No Firewire
The port was done based on logs and info received via private email. It
was only tested on the Acer G43T-AM3 so far, which still builds and works.
Change-Id: Ic2654ca4b198bfea409992be14e89702cf67ea50
Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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In preparation for CB:83968, rework the configuration files and move
files specific to G43T-AM3 to its own variant directory.
Change-Id: I425852f4bdacf7cb6688a5fb845ac3001373262e
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57764
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch calls `xhci_host_reset()` function to perform XHCI
controller reset.
Currently, the PMC IPC times out while sending the USB-C (0xA7) command
during poweron from S5 (S5->S4->S3->S0).
On Brya variants, poweron from S5 state results in PMC error while
sending PMC IPC (0xA7) to USB-C active ports, log here:
localhost ~ # cbmem -c | grep ERROR
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:0 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:1 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x20a0 failed
This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).
During poweron the state of USB ports are not the same between S5 and G3
and it appears that the active USB port still is in U3 (suspend) while
PMC tries to send the IPC command, which results in a timeout.
This patch utilises the S5 SMI handler to reset the XHCI controller
using `xhci_host_reset()` prior entering into the S5, it helps to
restore the port state to active hence, no PMC timeout is seen with
this code change.
Supporting Doc=Intel expected to release a TA (Technical Advisory)
document to acknowledge this observation and supported W/A for ADL
generation platforms.
Till that time, keeping this W/A as part of the google/brya specific
mainboard alone.
Note: other ADL-SoC based mainboards might need to apply the similar
W/A.
BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.
Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR
No PMC timeout error is observed with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Recently merged commit 8cc1d79ed0c3 (mainboard/qemu-aarch64: Get top
of memory from device-tree blob) missed a rebase and hence needs the
include path updated.
Tested `make qemu` for qemu-aarch64.
Change-Id: Id669eeaabbc1710bb7e408659f2d79f682427919
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
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Trying to probe RAM space to figure out top of memory causes an
exception on AArch64 virtual machines with recent versions of QEMU, but
we temporarily enable exception handlers for that and use it to help
detect if a RAM address is usable or not. However, QEMU docs recommend
reading device information from the device-tree blob it provides us at
the start of RAM.
A previous commit adds a library function to parse device-tree blob that
QEMU provides us. Use it to determine top of memory in AArch64 QEMU
virtual machines, but still fall back to the RAM probing approach as a
last-ditch effort.
Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80364
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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1.Set unused device's GPIOs to NC based on fw_config.
2.Disable config for nvme, ufs and CNVi based on fw_config.
3.Add fw_config STORAGE_UNKNOWN to enable all storages
for the first boot in factory.
BUG=None
TEST=emerge-brox coreboot chromeos-bootiamge
check fw_config messages in ap log
verify devices on/off by fw_config on jubilant
Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
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Locking GPP_F15 causes DUTs with fingerprint sensor to not be able to
correctly power down and stay powered down. This pin does not need to
be locked.
BUG=b:359692570, b:356750516
BRANCH=firmware-brya-14505.B
TEST=`FW_NAME=gimble emerge-brya coreboot chromeos-bootimage`, flash and
boot gimble into developer mode, then reboot into dev screen and select
the "Power off" button and verify gimble powers off and does not power
itself back up.
Change-Id: I1c73035b02021b0d1268cd46dcd0841621556ad5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83932
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The AP console log contains "HECI: No CSE device" and the system cannot be entered.
BUG=b:359474142
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
The "HECI: No CSE device" message for AP log disappered
Change-Id: I488056dc8bca2174dd96c28793e3202b7aae890c
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83905
Reviewed-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This reverts commit 2eb5c1e83ef5206f384846d7514c3aebcaec5bb8.
Reason for revert: The latest release of FSP will not boot
without a display being connected using this VBT. The original
VBT does not have this issue, nor is the original issue that
commit 2eb5c1e83ef5206f384846d7514c3aebcaec5bb8 fixed.
Revert it to restore booting when there is no display.
Change-Id: I05f9037cd68b8b29e69156e2372a544985f4442e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Extracted from coreboot-Google_Phaser.11297.296.0.bin.
Fixes display init on newer LASER14 boards.
TEST=build/boot google/phaser, observe display init successful.
Change-Id: Icb48edb4e74f147e3458f845d921a15a2d1906da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83897
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In next phase, riven will remove external fivr. Use the board version
to config external fivr for backward compatibility and show message.
BUG=b:359062365
TEST=build, boot to OS, suspend/resume work normally.
Change-Id: Id5f538b2eda7820a922b8d9ee14b2bae7df3726c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Brox does not have PCIe WWAN or discrete GPU. Hence no need to power
them off during suspend. Hence also remove the MPTS ACPI method.
BUG=None
TEST=Build Brox firmware and boot to OS.
Change-Id: Ia239c3f038ce31934efb0a391350fa0f786e3fcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83788
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brox uses Ti50 which always supports long interrupt pulse. Hence no need
to override GPIO PM.
BUG=None
TEST=Build Brox firmware and boot to OS. Perform suspend/resume for 25
cycles.
Change-Id: I6a138c1953714bc29570db587594cab8f315a4ec
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83856
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables the TCSS XHCI in the devicetree to solve the genesys
hub enumeration issue.
BUG=b:348332200
TEST=Able to build google/nova and ensure lsusb can list genesys
hub device.
Change-Id: Ic8e25756a2975e884434c4c7e3d587f4c1f0ed0b
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83845
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Confirm with EE, the GPP_C1 don't need PU 20K.
So modify GPP_C1 setting to remove PU 20k
Schematic version: 500E_GEN4S_ADL_N_MB_0418
BUG=b:358162951
TEST=Build and boot on pujjoga.
Change-Id: I7ad16cd29ab467d3eac74dab40522c577d91c747
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83818
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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1. The P sensor need follow WWAN FW_CONFIG to enable/disable
2. Modify GPP_H19 setting to PAD_CFG_GPI_APIC to fix PLT test fail
Schematic version: 500E_GEN4S_ADL_N_MB_0418
BUG=b:357998089
TEST=1. Boot to OS and verify the P sensor devices is set based on
fw_config.
2. Confirm that the PLT test can pass successfully.
Change-Id: Ic3610180c8cf99eba9367e26bfc3666410af19f7
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:348125053 b:348126380
TEST=emerge-nissa coreboot
boot with elan TS, make sure elan TS is functional.
Change-Id: I64c5a11dfaacfcca34240375d4dca5c76a60f62e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83876
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Turn on DRAM_LED on the mainboard in early bootblock, and turn it off
in ramstage. Primarily an indication if boot fails during raminit,
modeled after vendor firmware.
This LED is controlled by GPIO07 on the super I/O.
Boot tested on hardware.
Change-Id: I549b51375d1ef056d5fc01871bfe62d60b8a01cb
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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