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2022-06-02mb/intel/adlrvp: Set power limits dynamically for ADL-N SKUsVidya Gopalakrishnan
This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Ie49398b8a7de8d8cff3536eae6a5e893980f9c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-06-02mb/google/nissa/var/craask: Disable PCIe WLAN pinsTyler Wang
Craask uses CNVi WLAN, so disable the PCIe-related GPIOs. BUG=b:229040345 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7bcf041503dcee448758dac46b1c9711d0b02ba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-01mb/lenovo/w541/Kconfig: sort alphabeticallyPeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9cefa29738b42dd08cb00489ad6e8644e3fc405e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/t440p/Kconfig: remove duplicates and sort alphabeticallyPeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I47fded50377ab624e4bceb320a5e069a7f36c2fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/t440p/hda_verb: WhitespacePeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I92c167bf95e605e098324b9e80cfaab8f589dcab Reviewed-on: https://review.coreboot.org/c/coreboot/+/63995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/w541/hda_verb: WhitespacePeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I284a5e39ca4b0032ed0c8e3a92c095db319d1691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/w541/dsdt.asl: Remove redundant commentFelix Singer
Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: Ide938a40ed1f6869ee248ed46f6bf29f95649490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/t440p/cmos: Remove unused optionsPeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9bf95ed74468e283bab79a5f25aee758d37d926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/google/brya/var/agah: Enable EC keyboard backlightTony Huang
BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I90d9f2e298e54832bc077eae1c8be0e39c151d90 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-01mb/google/brya/var/kinox: Set memory SMBus addresses based on board revDtrain Hsu
Starting with id 2, boards switched the memory SMBus slave address, and use 0x50, 0x52. BUG=b:233975373 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I5e683ffdbc0727259ee796610cd97a6e378bf335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-01mb/google/corsola: Add new board 'steelix'Zanxi Chen
Add a new kingler follower 'steelix'. BUG=b:232195941 TEST=make # select steelix Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-01mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEGArthur Heymans
Tested with SMI_DEBUG: SMM prints things on the console. Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-01mb/google/brya/var/craask: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia288937ef3a4229088b60d87d31ea88057377a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-01mb/google/brya/var/nivviks: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: If2a77c0239646759e0192b72ba1991d334dd15aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-01mb/google/brya/var/nereid: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I47b069377046652ba4d278733a15bbca98bdb739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-01mb/google/brya/var/kinox: Add delay time for BH799BB rtd3Dtrain Hsu
This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:232327947 TEST=Build and suspend_stress_test -c 2500 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-01mb/google/dedede/beadrix: Add fw_config probe for ALC5682-VD & VSTeddy Shih
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BRANCH=dedede BUG=b:226910787,b:232057623 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I059b750743ab3b29d17c50d0d4301fbae4873acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2022-06-01sc7280: Improve performance by removing delays in cpucp initSudheer Kumar Amrabadi
As cpucp prepare takes 300 msec moving to before ramstage BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board observed total timestamp as 1.73 sec from 1.97 sec Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-05-31mb/starlabs/lite/glk: Don't configure GPIO's 147 through 156Sean Rhodes
These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia1bf4e32aa156a0e1a74df2f62eb31cdadb376a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/glk: Simplify GPIO macrosSean Rhodes
Use shorter macros to configure GPIOs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I91961658dca0902080576134e63e6d8a7c78d711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/glk: Disconnect unused GPIOsSean Rhodes
Disconnect GPIOs that are unused or not connected. Also, update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic83797b8a8e05eed99db0356f360a329f6fbf347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/google/nissa/var/craask: Generate SPD ID for supported memory partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. K3LKLKL0EM-MGCN BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ie022dd95929549ddd403d4c1d1c52174fd3fd721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-31mb/google/brya/var/kinox: Select VBT based on FW_CONFIGDtrain Hsu
Select vbt bin files based on DB_DISPLAY field of FW_CONFIG. BUG=b:233690293 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Idb92be66927259732bfd27e4db2c9f242da7d200 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-31mb/google/brya/var/taniks: Modify DPA value to 100 for taniksLeo Chou
In order to meet the OEM's acoustic specifications, the pre-wake randomization time (DPA) is set to 100. BUG=b:228410327 TEST=build FW and checked DPA value by fsp log. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Idaf3f931a2c0f2373445948e5f53a82328ec7ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-31mb/google/nissa: Add and default to 16 MB layoutKangheui Won
Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and make it default for nissa. BUG=b:202783191 TEST=build nissa and brya firmware, check they're still 32MB Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-31mb/lenovo: Rename t440p to haswellFelix Singer
In preparation to follow-up commits, rename the mainboard folder from t440p to haswell, which will have more variants later. Change-Id: I4a9d68d54d5f0821bbf85faaa620855d456c97f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-05-31mb/starlabs/lite/{glk/glkr}: Configure prt0_gpioSean Rhodes
PERST_0 is not used, so set this to GPIO_PRT0_UDEF (undefined) to ensure that an undefined address is not added to GNVS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac9b116b2fa28824a89db28911188364dc9a1a53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-30mb/asrock/h81m-hds: Reorder selects alphabeticallyFelix Singer
Change-Id: I18398efefcb4171496c39462c23514ad61659213 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-30mb/asrock/b85m_pro4: Reorder selects alphabeticallyFelix Singer
Change-Id: Ic22fcbb7923ecac4c70147ae642ac28fac3e6e6d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-30mb/lenovo/t530: Reorder selects alphabeticallyFelix Singer
Change-Id: I772ef94c860a26214bdae367d9863a56d5df9469 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-30mb/lenovo/t530: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I9940ad2e963458e4bc50c2a2957bb72cbd4109be Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-30mb/lenovo/t530: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I8ef0e67a8f26b98acea777afb26ed221bfa90153 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-30mb/google/brya/var/vell: Move SPK0/SPK1 to I2C7eddylu@ami.corp-partner.google.com
To support speaker AMP CS35L53-CWZR'S I2C needs to split to two I2C ports BUG=b:207333035 BRANCH=none TEST=built and verified speaker Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com> Change-Id: I8095abc4fc3233b21b818a508c84cd59b39fc1d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
2022-05-30Revert "mb/google/brya/var/vell: Remove unused i2c7 settings"Shon Wang
This reverts commit bd9cec8ae5755e898d107fd061fc2e2f983552b9. Reason for revert: Enable i2c7 for amp changing to 2 channel because vell setting amp on i2c0 and i2c7 on next phase BUG=b:229334701 TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend && checks EC log and ensures the DUT could enter s0ix. Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Change-Id: I5988cd9926b2c9ced1d111774abaa897bef91537 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-30mb/google/brya/var/kinox: Correct the target of DPTF active policyDtrain Hsu
Kinox has four temperature sensors. Modify the target of DPTF active policy to map correct temperature sensor. BUG=b:231380286 TEST=Boot to Chrome OS and doesn't see "DPTF: Invalid sensor ID" from ec comsole. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Icb5c285a6f483e2a1b6510a962ff7f7f6e9a79e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-29mb/biostar/a68n_5200: Use pci_or_config8()Elyes Haouas
Change-Id: I4be0a4ad980b4167eaaafc22399b680abf011553 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29mb/google/brya: Increase Resizable BAR address space limit to 32 bitsTim Wawrzynczak
The dGPU used for some Brya projects requests 32 bits of address space for one of its BARs via the Resizable BAR mechanism. This Kconfig is currently set at 29 bits for brya, so the allocation currently is capped at 29 bits. This patch sets the limit to 32 bits for brya boards, which is enough for the GPU. BUG=b:214443809 TEST=all of the dGPU PCI BARs on agah can be successfully allocated Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I61dbe47f1f316967d052bae748ff23babde61ef0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29mb/google/brya/var/agah: Fix GPU power sequencingTim Wawrzynczak
While testing the power sequencing code for the GPU, a few mistakes were found. This patch fixes those errors: 1) FBVDD load-switch enable is active-low 2) NVVDD VR enable is active-high 3) GPU_PERST_L should be driven low during GPIO table programming 4) The BAR saving code missed the top 32 bits of 64-bit BARs 5) sequence_rail() assumed the pwr_en_gpio and pg_gpio were the same polarity 6) PEG vGPIOs were not programmed to the correct NF BUG=b:233552225 TEST=dGPU is able to successfully enumerate over PCIe bus Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I85767d382012a0c7dfdb1f849768e0160f06c273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-29mb/google/brya/variants/felwinter: Enable Bluetooth offload supportMac Chiang
Add fw_config support NMAX98360_ALC5682VS_I2S_2WAY and I2S2 vgpio config and enabling cnvi_bt_audio_offload UPD bit. BUG=none TEST=emerge-brya coreboot Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I64a4e5479905911b2e9d1597b78131720abb689e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-28mb/starlabs/lite/glk: Remove unnecessary DPTF UPDSean Rhodes
The default for DPTF is off (0), so remove the entry that sets this to off. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0397ff6f71766a2f738ab2b71be298ef8f2b1c9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Remove unnecessary parametersSean Rhodes
Since using FSP 2.2.0.0, the defaults match the required settings so they no longer need to be specified. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie0e00cae67cb89b184392e97b8ec196d45ea5d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/google/brya/var/agah: Update USB-C port settingIvy Jian
Correct the USB-C port setting according to schematics. AP log: port C0 DISC req: usage 1 usb3 3 usb2 1 port C1 DISC req: usage 1 usb3 1 usb2 3 BUG=b:233554817 BRANCH=brya TEST=emerge-draco coreboot chromeos-bootimage Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Iea4aee19dff8e0bc863be46532f89e81f52f281b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/mithrax: Update typeC EC mux portJohn Su
We need to put USB setting in mux order. BUG=b:234103724 TEST=Type C mux configuration is correct. Wrong: added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Correct: added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f8dbee35159960d17107e23fcde825a38c7de4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/starlabs/labtop: Add LabTop Mk IIISean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iii-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ben McMillen <ben@starlabs.systems>
2022-05-28mb/google/brya/var/volmar: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 | MLB DB | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ibd36fb961de9e9af9da1fd885eeb958c833d38bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/taniks: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia66c6fafe08110b8d8f9a138a2516ae03f8e1809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/{taeko, taeko4es}: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Icd56c650a03c5db6e1e68e4ca4c9f0c068a7a430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/{primus, primus4es}: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | A0 C0 | MLB DB | A | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia493fd28c362d2c0c343c2d121f6611cfd8f7f6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/kano: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 | | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I840b0f363a1ff304b310505efdaba2ac1cd10472 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/felwinter: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | C1 | MLB DB | A0 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ie4f96e3636a8b519923fdba7f9bd07d7a3e1d7ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/64613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/{anahera, anahera4es}: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ A | | A C0 | MLB DB | C2 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia1e95aba2f7d02131b0b0cdd6c7211a23e355084 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/{brya0, brya4es}: Correct _PLD valuesWon Chung
This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C2 | | A0 C0 | MLB DB | C1 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I68fb940825bfcf7c77ca3015372025e47e7fcc41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/brya/var/nissa: set tcc_offset value to 10Sumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature as mentioned in doc #572349. BUG=b:229804441 BRANCH=None TEST=Build FW and test on Nivviks board Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-28mb/google/skyrim: Update Kconfig to use Ti50Jon Murphy
Skyrim uses the Ti50 GSC and the config should be updated to reflect that. BUG=b:233750667 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5d4af19ab2dda35ab687a0659898d79b08c4de97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-28mb/starlabs/lite: Add Bluetooth USB interfaceSean Rhodes
Enable the USB port that is used by the Bluetooth interface on the CNVI. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2a330618c5f1c5fd5e3147cb6307c157b28070ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/64545 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite: Remove webcam USB port from devicetreeSean Rhodes
Remove the Webcam USB port form the devicetree and handle it solely in devtree, which will enable or disable it based on the CMOS option. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c89c7103aca5c3d42215122e9d94c83947b6fee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28mb/starlite/lite: Configure tcc_offset based on power_profile settingsSean Rhodes
Set tcc_offset value based on the power_profile value, ranging from 5 to 15 degrees. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id30bec9c095517884a7361226aed703b370f2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28vendorcode/amd/agesa/fam16kb: Fix improper use of .dataArthur Heymans
AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-05-28vendorcode/amd/agesa/f15tn: Fix all improper use of .dataArthur Heymans
AGESA has a lot of code in the .data section which is for initialized data, that in fact should be .rodata. This adds the 'CONST' keyword everywhere it is needed. TEST: See in the .elf file (e.g. using readelf) that there is nothing in .data section. Change-Id: I9593c24f764319f66a64715d91175f64edf10608 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-05-28mb/google/brya/var/vell: Set empty on USB2_9/USB32_1Shon
The baseboard uses port USB2 #9, and USB3 #1, but vell does not, therefore set the port configuration to EMPTY. Change-Id: I0d03b967fd2a051205ad5807f0bd8916bad7c036 Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-28mb/starlabs/lite/{glk/glkr}: Disable PMC PCI deviceSean Rhodes
The PMC is accessed via sideband registers, so the PCI device is not needed. Disabling it solves a bug where the laptop cannot be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I78f4aa4567dfc154ef5cb21f8746265259cd53e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64451 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite/{glk/glkr}: Disable DPTF deviceSean Rhodes
DPTF is not used, so disable the corresponding PCI device. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9e4a3bada13dcabc1af3e1e5b3c215939f8239fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Remove subsystem device IDSean Rhodes
Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I63d6a4b0f19d400d683cab5dacca787d6c6a0fdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-05-28mb/starlabs/lite/{glk/glkr}: Decrease S3 assertion time to 28 msSean Rhodes
Set S3 assertion time to 28000us as this is sufficient time for rails to discharge. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a14e7b30bb1fc4c0c1d3ff2f75069863458487f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64447 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-28mb/starlabs/lite/glkr: Correct OverCurrent PinSean Rhodes
The USB ports use both OC0 and OC1. Whilst they work perfectly with OC_SKIP, set them to the correct pins. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If173b443d9770083d76519b854b513d8e47b9e71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-28mb/starlabs/lite/glk: Correct OverCurrent PinSean Rhodes
The OC pin was set to 0, which isn't connected. All USB ports are connected to OC1. This solves a strange issue where the Lite can't be powered on without the charger connected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I700ddde291f0e4be6e3787e2da13f6d3ece736b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28mb/google/brask/variants/moli: correct empty tcss portRaihow Shi
Correct empty tcss port to meet Moli's schematic design. BUG=b:233834605 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Id16744655010e246c8ca8d1050f71a6c6c63d2a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-28mb/google/brya/var/banshee: Enable SaGvFrank Wu
Enable SaGv support for Banshee BUG=b:233930777, b:233703655 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I22810f422e3f1d6dd1f64d93e6d7aff5593ff739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2022-05-26soc/intel/tigerlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard starlabs/laptop/tgl, since it is obsolete now. Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-26soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the following mainboards, since it is obsolete now. * siemens/chili * starlabs/laptop/cml Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-25mb/google/brask/variants/moli: enable USBA port 4Raihow Shi
Moli has USBA port4 but Brask didn't use the port4, so enable USBA port4 in moli. BUG=b:232656163 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I5308e3102ea9f0718802596a235c0a5cc42e30bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-25mb/google/brya/var/mithrax: Add WiFi SAR table for mithraxJohn Su
Add WiFi SAR table for mithrax. BUG=b:231491014 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I847debd7c817225b5b1777c798a14ef10aee3471 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-05-25mb/google/guybrush: Remove unused GPIO tableJon Murphy
On Guybrush, the power and lid switches are managed by the EC and coreboot and the AP have no control over them within this context. Remove unused GPIO's to prevent coreboot warnings about resampling at boot. BUG=b:233771033 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I1c68fce817a2a98ce0e8f1d9771d6c630dd5e88a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-25mb/google/skyrim: Update DDI descriptor for HDMIJon Murphy
The HDMI port was specified as a display port. Update to allow for testing of 4k streaming. BUG=b:229771029 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ib4dc8a5c6110630cea768f81e34fd7b0a5a62657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-25mb/google/skyrim: Remove unused GPIO tableJon Murphy
On Skyrim, the power and lid switches are managed by the EC and coreboot and the AP have no control over them within this context. Remove unused GPIO's to prevent coreboot warnings about resampling at boot. BUG=b:233771163 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie369bb7d430bd0dd1f1c1f41bf543a9b18e34db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64644 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-25mb/google/guybrush: Remove unused sleep GPIO tableJon Murphy
On Guybrush, there wasn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function calls/overhead. Missed changes to variant.h in initial commit(already merged) BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idba1a9eeea5ea5f5922281668ec17c4f065a654d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64643 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-25mb/google/brya/var/taeko: Modify DPA value to 100 for taekoleo.chou
In order to meet the OEM's acoustic specifications, the pre-wake randomization time (DPA) is set to 100. BUG=b:232892200 TEST=build FW and checked DPA value by fsp log. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I65e3fef581ee06fa049e831f246da1328a08518c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-25mb/google/brya: Replace space with tabSubrata Banik
Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3dfc5862fdcc663d9e0adbfda30c940d43b49b4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-25mb/google/kukui: Add LPDDR4X MT53E2G32D4NQ-046 WT:C supportKevin Chiu
Separate and add LPDDR4X MT53E2G32D4NQ-046 WT:C support for burnet/esche ID#1: MICRON - MT53E2G32D4NQ-046 WT:C BUG=b:225121354 BRANCH=none TEST=1. emerge-jacuzzi coreboot 2. power on test ok Change-Id: If720d7bcf185c5c0149a82125ec068fc75e5b3cd Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64069 Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-25mb/google/nissa/craask: Change pen garage wake to EV_ACT_ANYTyler Wang
Follow google stylus spec. The Stylus-Present GPIO MUST be a wake pin that interrupts the system in active operation when the stylus is removed or inserted. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Id6ee977fbda3118229677aa76e5394f5592c3da8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-24mb/google/skyrim/baseboard/devicetree: enable S0ixFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6c5b3f83b66a2d54611ada3cb97ddda4b655d00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64606 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/amd/chausie,majolica: don't select HAVE_ACPI_RESUMEFelix Held
The Chausie and Majolica boards use S0ix which is mutually exclusive with S3, so don't select HAVE_ACPI_RESUME. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d1bf33ad017dfbf908e0a195949998668c8e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64605 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya: Set eMMC dll tuning parameters for NissaUsha P
Add support for MB level dll tuning. This patch sets the eMMC dll tuning parameters to default values needed. There was issue observed on some eMMC devices which failed to boot in HS400 mode.EV team suggested the intermediate eMMC dll tuning parameters that needs to be set. We observed these values helped to fix the issue. While we get the verified default values set from FSP directly, adding it here to use it as the custom dll values needed. BUG=b:230403441 TEST=Build and boot nivviks board. Verify the eMMC dll parameters are overridden. [INFO ] usha: After override dll_params [INFO ] usha: emmc_tx_cmd_cntl=505 [INFO ] usha: emmc_tx_data_cntl1=909 [INFO ] usha: emmc_tx_data_cntl2=1c2a2828 [INFO ] usha: emmc_rx_cmd_data_cntl1=1c1b1d3c [INFO ] usha: emmc_rx_cmd_data_cntl2=10049 [INFO ] usha: emmc_rx_strobe_cntl=11515 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I27771b663ce9808e5a5ef4b36c136ad78f924376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-05-24mb/google/brya/var/kinox: Set the physical location of each USB portDtrain Hsu
Set custom_pld of each USB port (both Type A and C) with actual physical location values. BUG=b:214025396 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ic84b9aae1501e36c2794382aabcf8225eef7783b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Won Chung <wonchung@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-24mb/google/brask/variants/moli: Remove stop pin declaration for LANRaihow Shi
Remove the stop pin declaration for LAN. Confirmed with LAN vendor, 8111K do not need to implement stop pin. It caused S0ix fail. BUG=b:231400227 TEST=Build and suspend_stress_test -c 5 pass Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Iae33068c4622f91d5cebb867e4b10f3834ce8bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-24mb/google/brask/variants/moli: add fw_config for usb retimerRaihow Shi
add USBC0_RETIMER into 2, 3 bits for usb retimer. BUG=b:232486478 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idaf2e53387476d344d2c838a6e762f5a4c582989 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-24mb/google/brya/var/kinox: Update the DPTF parametersDtrain Hsu
Follow the Thermal_paramters_list-0520.xlsx to modify DPTF baseline PL1 values. 1. Modify baseline PL1 min_power from 15000 to 12000. 2. Modify baseline PL1 max_power from 17000 to 25000. BUG=b:231380286 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibd3098ee6bbf964cffddfcc9a4600cb7d81162d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64595 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ricky Chang <rickytlchang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya/variants/nivviks: Add DPTF passive and critical policies for ↵Vidya Gopalakrishnan
Nivviks Add DPTF passive and critical policies for ADL-N Nivviks design. Temperature threshold for triggering Passive Policy is set to 75C and Critical Policy is set to 85C respectively for TSR0/1. BUG=b:224884901 BRANCH=None TEST=Build FW and test on Nivviks board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Change-Id: I5c9b9e8c2489c7da501ca136e2aa6fbc764bf400 Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64466 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24mb/google/brya/baseboard/nissa: Enable DPTF for Nissa variantsVidya Gopalakrishnan
BUG=b:224884901 BRANCH=None TEST=Build FW and test on Nivviks board Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-05-24mb/intel/ehlcrb: Adjust TSN GBE settings in devicetreeLean Sheng Tan
Set PCH TSN link speed to 1 Gbps and enable MultiVC for all TSN ports. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8d43c3ba8f02645c8ad2993f76e610d838b0151a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-05-24mb/google/brya: Create kuldax variantDavid Wu
Create the kuldax variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:233380254 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KULDAX Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I95c04768bbed8657d2858bcd66fc041f56910b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-24mb/google/brya/var/volmar: Add wifi sar tableRen Kuo
1. Add wifi sar table for volmar 2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG BUG=b:233319626 TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I09069bbc3a41b66ec9a88cfede46acc067209b01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2022-05-24mainboard/google/corsola: Fix incorrect timestamps in the eventlogYidi Lin
Timestamp '2000-00-00 00:00:00' is considered as the invalid format. Enable RTC to fix incorrect timestamp format in the eventlog. BUG=b:232035991 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: I8d9822075377734ef4a609ddeee79385fe7af0f0 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
2022-05-23mb/siemens/mc_ehl: Disable RAPLUwe Poeche
Disable RAPL for all mainboards based on mc_ehl for stable real time mode of CPUs. Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR register are cleared. Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-22mb/google/guybrush: Remove TODO for ESPI functionsJon Murphy
The feature request was moved to Skyrim in the interest of time and effort. The bug was updated to reflect this, and the comment should be removed from the monkey island code base BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id4ca43692aa56b6dba2f7acc1f924b30c1e966ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/64558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-22mb/google/guybrush: Remove unused sleep GPIO tableJon Murphy
On Guybrush, there wasn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function calls/overhead. BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic51ee4845d663acf34f050f7b3abf57a7c247c88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-21mb/gogle/skyrim/devicetree: enable display HDA deviceFelix Held
The HD audio controller of the GPU on bus A device 0 function 1 wasn't enabled, so it didn't get resources assigned. Enable it to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib9a4129ce594c5dd59f70e855fef5f2c04ebb9c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64554 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/gogle/skyrim/devicetree: enable audio coprocessor deviceFelix Held
The ACP device on bus A device 0 function 5 wasn't enabled, so it didn't get resources assigned. Enable the ACP device to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc9376314213e9d624756519f703d508411cb1bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/64553 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/gogle/skyrim/devicetree: enable crypto deviceFelix Held
The crypro device on bus A device 0 function 2 wasn't enabled, so it didn't get resources assigned resulting in this the Linux kernel error: [ 38.582036] pci 0000:04:00.2: attach allowed to drvr ccp [internal device] [ 38.582064] ccp 0000:04:00.2: enabling device (0000 -> 0002) [ 38.582175] ccp 0000:04:00.2: ioremap failed [ 38.582178] ccp 0000:04:00.2: initialization failed [ 38.582181] ccp: probe of 0000:04:00.2 failed with error -12 Enable the crypto device to fix this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia812df6e59f3767dcbaa908fa620b62619590f85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64552 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-21mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edgeMario Scheithauer
There are three external Marvell PHY 88E1512 on this mainboard. The PHY IRQ comes with a falling edge but the EHL MAC side needs a rising edge signal. For that reason, we need an inversion of the IRQ polarity. Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 01:39:45 +0000