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2023-09-01mb/google/rex: Add `rex4es_ec_ish` variantBernardo Perez Priego
This patch creates rex ES variant with EC ISH enabled. BUG=b:296886409 TEST=Able to build and boot rex4es_ec_ish variant. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I2b1cdb8cffd66badd90a7bf9825d9decb07941a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-01mb/starlabs/starbook/rpl: Disable dynamic Tc-cold handshakeSean Rhodes
With the Tc-cold handshake, there's a fast flicker when connecting external displays. With it disabled, it's just one "flick", so use this as it's lesser of two evils. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie42b935d3e69beff6a1e503a8dee69554123b4f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-09-01mb/msi/ms7d25: Configure ASPM and Clock PM based on KconfigMichał Żygowski
Add support for FSP ASPM and Clock PM configuration based on Kconfig options: PCIEXP_ASPM, PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE. For some use cases it may be desirable to disable ASPM and Clock PM to achieve more deterministic and higher performance of PCIe devices. TEST=Boot MSI PRO Z690-A DDR4 without ASPM and Clock PM. Confirm all PCIe devices are still working and ASPM and Clock PM capabilities are not present on the PCIe Root Ports. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6d9d11016bed89dcfee6909d0d3e3e2e56237a2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69825 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao
It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-31mb/google/dedede/var/pirika: Add FW_CONFIG probe for EXT_VRDaniel_Peng
Add FW_CONFIG probe for absent FIVR bypass mode on peezer. BUG=b:296982082 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: I0b2053b2d732fd9462686ed7b0c9225539b28fb2 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77396 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-31mb/google/rex/var/karis: Update GPIO settings for NC pinsTyler Wang
According to the schematic, set below GPIO to NC: 1. GPP_C18 2. GPP_C19 3. GPP_S04 4. GPP_S05 BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: If1f847d2db83b63a351203f0449cc1368bef27f4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77558 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-31mb/google/rex/var/rex0: Add HDMI GPIOs to early GPIO listAnil Kumar
Add HDMI GPIO configuration to early GPIO list to support VGA text o/p in Pre-RAM stage on HDMI. BUG=b:279173035 TEST=If CONFIG_UGOP_EARLY_GRAPHICS is set to y, check SOL text on HDMI during Pre-RAM boot stage. Change-Id: I13691850d09a442d5d5493a2b1dcf1145cf9797a Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-31mb/google/rex: Enable Fast V-Mode for MTL-U 15WSubrata Banik
This patch sets the Fast V-Mode (FVM) configuration parameter as suggested in Intel doc 640982. As per the doc, Intel MTL-U 15W CPU supports FVM on IA and SA. Fast V-Mode (FVM): Intel Meteor Lake introduces the ability to manage the peak power events it calls "reactive peak power management". The Fast V-Mode is one such technique to perform the reactive peak power management. It relies on the detector integrated inside the processor which senses when the processor load current exceeds a present threshold by monitoring the processor power domain IMVP (Intel Mobile Voltage Positioning) VR sense point. The baseline ITRIP for IA is 66A and 21A for SA. BUG=b:286809233 TEST=Able to build and boot google/rex without seeing any performance regression. Change-Id: Ia7157bddf2e9586e4a91cc55e48693561072cd05 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75763 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-30mb/google/rex/var/karis: Remove USB cameraTyler Wang
Karis use MIPI camera only, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I96316d63c068c48b5bec75d3b4c5444d15fd985f Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77510 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-30mb/google/rex/var/karis: Remove SAR sensorTyler Wang
According to the schematic, karis does not have a SAR sensor. Update GPIO settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ib3b66b9594f2d0fddbbfc56e99f06b6587487f2a Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-30mb/google/rex/var/karis: Set GPP_D04 to NCTyler Wang
Follow schematic, set GPP_D04 to NC. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie222a2773ff7d2b87641f55b4d37ff3bdf761cd2 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-30mb/google/rex/var/screebo: Enable GL9750 invert WP functionKun Liu
enable GL9750 invert WP function BRANCH=none BUG=b:297244291 TEST=emerge-rex coreboot Change-Id: I7fdc94b5ca6b316ee0291c38e39c5f8b08cbc127 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77414 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28Revert "mb/google/brya: fix MRC cache failure for hynix parts"Nick Vaccaro
This change causes a freeze during boot on an RPL-UR that does not have the memory part string in the CBI. BUG=b:296353047 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage', flash and boot problematic DUT to kernel. This reverts commit c51a7cdde4e1cb9014be401136c3f07f220ef365. Change-Id: I99fe5111b5294673d9e0a5d13f9c240e0f4a92c3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77516 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: <srinivas.kulkarni@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-28mb/google/rex/var/rex0: Enable BT offload audio for Intel MtP2 moduleAnil Kumar
Enable the required GPIO and FW_CONFIG support to configure BT offload audio in discrete mode for Intel Mysty Peak module on google/rex Proto2 HW. BUG=b:297125514 Test=Verified BT audio playback on google/rex Proto2. Change-Id: I560f1700f78f8b653dfcc2f26764f0ebf2652689 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77357 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-28mb/google/rex/var/karis: Remove UWBTyler Wang
According to the schematic, karis does not have a UWB, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I8a442518c2007cde883183871cef96db416850c0 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77437 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-26mb/system76: Enable DRIVERS_GENERIC_BAYHUB_LV2 to fix LTR issueJeremy Soller
Clevo started using OZ711LV2 for the SD card reader around the time of making its TGL boards. Without the driver, CPUs don't go to power states lower than C2 due to LTR not being programmed. After enabling the driver the CPU will go to C8 while the system is idle, giving significant power savings if the system is left on battery power. There is another issue with RPL where it only goes to C6 instead of C8. This may be due to the intel_idle driver in Linux (as of 6.5-rc6 mainline and 6.4.6 stable) not supporting RPL C-states. - tgl: Started being used with the Gazelle 3060 variant - adl: Used on all models - rpl: bonw15 does not have an SD card reader Change-Id: I85c60feb6dcae7d877e70a6c6f2d3a7b3296fa0e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/rex/var/karis: memory: Add Micron MT62F512M32D2DR-031Tyler Wang
Add new memory part in the mem_parts_used.txt and generate the SPD ID. 1. MICRON MT62F512M32D2DR-031 WT:B BUG=b:291018417 TEST=emerge-rex coreboot Change-Id: I6e05c0d41a4899ed64dbab7efd8904cd361cb50e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77426 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/dedede/var/taranza: Add Wifi SAR for taranzaSheng-Liang Pan
BUG=b:297276380 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Cq-Depend: chrome-internal:6373154 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-08-26mb/google/rex/var/karis: Remove WWAN moduleTyler Wang
According to the schematic, karis does not have a WWAN module, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/rex/var/rex0: Use FW_CONFIG to select the correct SAR tableSubrata Banik
This patch changes the SAR table selection logic to use FW_CONFIG which will eventually help to support different WiFi SAR tables. TEST=Able to build and boot google/rex. Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de Signed-off-by: YH Lin <yueherngl@google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-26mb/google/nissa/var/yaviks: Disable SUSCLK based on fw_configWisley Chen
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage. BUG=b:296511904, b:294456574 BRANCH=firmware-nissa-15217.B TEST=build and verified by EE Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/brask/var/kuldax: Set customized_leds value for RTL8111KDavid Wu
Set customized_leds value for RTL8111K to fix led can't work. BUG=b:297093096 BRANCH=firmware-brya-14505.B TEST=Verified RTL8125 and RTL8111K led can work normally. Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/google/brya: Create nokris variantChen-Tsung Hsieh
Create the nokris variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:285838647 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOKRIS Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35 Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-25mb/google/rex/var/ovis: Update PWM_BUZZER GPIO configJakub Czapiga
BUG=b:271491845 TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08 Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-25mb/google/nissa/var/joxer: set the DB_USB field in FW_CONFIGMark Hsieh
Joxer will have SKUs with no type-c on daughter board, add fw_config for EC control it. BUG=b:297131468 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-25mb/amd/birman: Enable two USB4 xHCI controller devicesAnand Vaikar
TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command 00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0 00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1 Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-25mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio tableTyler Wang
Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage gpio table. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-25mb/google/rex/var/karis: Fix incorrect GPIO pad numbersKapil Porwal
Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of GPP_F14, GPP_F15 and GPP_F16 GPIOs. BUG=none TEST=none Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/hp/compaq_elite_8300_usdt: enable mSATARiku Viitanen
Tested with a Kingston UV500. It works the same (3Gb/s) as with vendor FW. According to smartctl -a /dev/sda: SATA Version is: SATA 3.1, 6.0 Gb/s (current: 3.0 Gb/s) Change-Id: I5c714351586e6084029ce4c54fb47cbae4d3405b Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77376 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-24mb/siemens/fa_ehl: Remove RTC RV3028C7Johannes Hahn
Delete this RTC from the configuration as fa_ehl mainboard uses a different real time clock. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2023-08-24mb/siemens/fa_ehl: Remove TPMJohannes Hahn
The mainboard currently does not make use of a dedicated TPM. Although it has one assembled. This TPM is not connected via LPC hence it is turned off in the devicetree. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-08-24mb/siemens/fa_ehl: Remove NC_FPGAJohannes Hahn
fa_ehl mainboard does not make use of the SIEMENS NC_FPGA as it is not placed on this board. Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-08-24mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED configStanley Wu
Enable bit 9 for 100M mode green LED blink. Reference: - RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration BUG=b:293983804 TEST=emerge-dedede coreboot and verify LAN LED behavior Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-24mb/google/nissa/var/yaviks: rename DB_NONE to DB_1AWisley Chen
Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko. BUG=b:294928078, b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Icb952c0716d446d5feb5580f357120a27193284e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mainboard/siemens/fa_ehl: Add new mainboard based on mc_ehl2Johannes Hahn
Add a new mainboard called fa_ehl which is based on Siemens's 'mc_ehl2'. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Moreover a variants scheme is provided for possible alternative implementations. Follow-up commits will introduce the needed changes for the new mainboard. Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6 Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2023-08-24mb/google/brya/var/vell: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/taniks: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/taeko: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/volmar: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/primus: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/osiris: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/omnigul: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/mithrax: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/rex/var/karis: Disable GSPI0Tyler Wang
According to the schematic, karis does not have a SPI touchscreen, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-24mb/google/brya/var/marasov: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/kano: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/gimble: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/felwinter: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/crota: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/banshee: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-23mb/amd/mayan: Enable the DT and M.2 SSD1 PCIE slotsAnand Vaikar
Program the EC GPIOs to enable the DT or M.2 SSD1 PCIe slots based on the config option selected. Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-23mb/google/brya: Create quandiso variantRobert Chen
Create the quandiso variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_QUANDISO Change-Id: I846c39260e2db504d7bec6e81a8317b6824c17f4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23mb/google/rex/var/karis: Remove WWAN temperature sensorTyler Wang
According to the schematic, karis does not have a WWAN temperature sensor, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ic82c6cfec067faa37d452bed5c4977402a2139a5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77284 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23mb/google/dedede/var/pirika: Add USB2 PHY parameters for Type-A/Type-CDaniel_Peng
This change are added fine-tuned USB2 PHY parameters to improve the USB2 eye diagram result. BUG=b:296493887 BRANCH=firmware-dedede-13606.B TEST=Local build bios successfully. And verified the USB2 eye diagram test result. Change-Id: I915fe689883267901e8faba28632345d8c227c28 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-23mb/google/brask/var/constitution: Separate wifi sar tableMorris Hsu
Separate constitution and intrepid wifi sar table in variant.c BUG=b:291859402 BRANCH=firmware-brya-14505.B TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I0f89b3d5f5252a2b55bad4d91ad4ab9ec7519c50 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77242 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-22mb/google/brya/var/bb/brask: enable HDMI gpios earlyNick Vaccaro
Add some HDMI-related gpios that are needed for early sign-of-life to the early_graphics_gpio_table array so that SOL will show up on HDMI ports. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds without error. Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21mb/google/rex/var/karis: Remove world facing cameraTyler Wang
According to the schematic, karis does not have a WFC. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I9b4ecf2e96c77c131a60e48614d792370dd33423 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-21mb/msi/ms7e06: Add support for MSI PRO Z790-P DDR4/DDR5 (WIFI)Michał Żygowski
TEST=Boot Ubuntu 22.04 on MSI PRO Z790-P (DDR5 variant) with Intel Core i5-13600K using UEFI Payload. Change-Id: Id2c77621d24bb097b930342eb1961270854d5f68 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76325 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21mb/google/skyrim/var/crystaldrift: drop commented out line in DTMatt DeVillier
Line is a duplicate, commented out. Drop it as it serves no purpose. Change-Id: Id35bdea0915ca47cac4f38ede6ccbf2f2fb59f47 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77304 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20mb/intel/mtlrvp: Disable C1-state auto demotion for mtl-rvpSukumar Ghorai
C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter PC2 and lower state in camera preview case and save platform power. Note: C1 demotion heuristics used EPB parameter to balance between power and performance, i.e. low threshold when EPB is low in-order to get C1 demotion faster and vice-versa. ChromeOS operates at default EPB=0x7 (low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits than expected (similar to AC mode) and losing power respectively. ref. https://review.coreboot.org/c/coreboot/+/76827 BUG=b:286328295 TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also verified PC residency improvement ~10% in camera preview case. Change-Id: I1b2db634176f0072c535608c5600846a9086fef1 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-20mb/intel/archercity_crb: Set SMM console log level via VPDJohnny Lin
Change-Id: Ic7d51037d527f95e8664ad04e328fc27901cacde Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71993 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20mb/google/rex: include Elan HID over SPI ASL for Rex4ESEran Mitrani
Existing code did not include the HID over SPI for rex4es. This CL corrects this issue. BUG=None TEST=Tested on Rex Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I02f7c4b68cfee2ebb202581c9f031af99ab4b6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77245 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/brya: Alphabetize board listings in Kconfig.nameMatt DeVillier
Change-Id: I551d71d968abb6a9cadbc0f87bc9258768db1fca Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77275 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/brya: Alphabetize selections inside Kconfig.nameMatt DeVillier
Change-Id: I7ed982c9dcf755c97f26cc43b3dc05b898e4150a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77274 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/brya: Add VBT data files for variantsMatt DeVillier
Add data.vbt files for all variants supported by current brya, brask, and nissa recovery images. Select INTEL_GMA_HAVE_VBT for all variants which currently have a VBT file. TEST=build/boot various brya variants (banshee, osiris, redrix) Change-Id: Ic66f91e264d37c3742cb17994f637604d77a1576 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77144 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/rex: Dump ISH version for `rex_ec_ish` variantSubrata Banik
This patch selects `SOC_INTEL_STORE_ISH_FW_VERSION` config to dump the ISH version as part of the .final hook. BUG=b:285405031 TEST=Able to build and boot google/rex_ec_ish. Verify the ISH version is same as MFIT ISH version section. > cbmem -c | grep "ISH" [DEBUG]  ISH version: 5.6.0.28821 Change-Id: I052af85ad836ab81ff6c510bb74e042b11940a65 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77178 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/poppy: add libgfxinit support for variantsMatt DeVillier
Add libgfxinit support for Nami, Nautilus, and Soraka. Panel timing values taken from default panel selection extracted from the respective VBTs. TEST=build/boot nami w/edk2 payload and libgfxinit selected Change-Id: If0ca389487338c47f9d8de990acf591c6907eaa9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77268 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-18mb/google/dedede: Add ACPI display brightness supportMatt DeVillier
Add support for ACPI display brightness controls, so that panel adjustment is available under Windows. TEST=build/boot Win11 on google/magpie, verify panel brightness controls available and functional. Change-Id: I66daa6bbca15046994dff83bee6e7cf99aae0b33 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77271 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/fizz/endeavour: update VBTMatt DeVillier
Update VBT with file extracted from FW_MAIN_A region of firmware file bios-endeavour.ro-13259-80-0.rw-13259-144-0.bin TEST=build/boot endeavour Change-Id: Ibf7b35c4e59c6fe816cf036e637483de75d6ecd4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-18mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control BUG=b:291217859 TEST=emerge-rex coreboot Change-Id: I6e6ad653157dc87a7d87b5ffc4f9590991a7c284 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76678 Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/volteer: Add ACPI display brightness supportMatt DeVillier
Add support for ACPI display brightness controls, so that panel adjustment is available under Windows. TEST=build/boot Win11 on google/drobit, verify panel brightness controls available and functional. Change-Id: Ic0c026ae09b3fde648db4bdeb4971423953c96a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77143 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex: Update ISH GPIO's configurationBernardo Perez Priego
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled, loaded, and functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I778251aadef4499427fc9855adfdd9cade3a3e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77235 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/starlabs/starbook/rpl: Fix the Thunderbolt cmos optionSean Rhodes
For Thunderbolt to be disabled, `UsbTcPortEn` and `TcssXhciEn` also need to be disabled. Change-Id: Ie02c1e0ea7583bbd78e25c8184e2cdf2b6281741 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-17mb/google/brya: Allow to show early splash screen using GFX PEIMSubrata Banik
This patch chooses to show the early splash screen which is an OEM feature. The current implementation is relying on the Intel FSP GFX PEIM to perform the display initialization. Having this feature allows the platform to show the user notification with 500ms since boot compared to traditional scenarios where first user notification is coming from kernel (typically ~3sec+ after cpu reset). Eventually this feature will help to improve the user experience while booting Intel SoC platform based chromeos devices. BUG=b:284799726 TEST=Able to see the early splash screen on google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2449bf97d6c82cb08f603b29643cc261738b5379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17mb/google/nissa/var/yaviks: Disable SD card based on fw_configWisley Chen
Disable pins for SD card based on fw_config. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I0b383d1b00056a69ba925bb5203dc4ca026b9d8e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77105 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Update USB settingsTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ia4bd6fe02ffa62ed8aeffb188de5c4c4b64900ff Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77106 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-17mb/google/rex/var/karis: Remove SD card and ISHTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I1575ee1d7e4c834ad15f60a3b7d63c041a8d4890 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77007 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Modify SSD settingsTyler Wang
Follow schematic, modify SSD related settings. BUG=b:294155897, b:289880020 TEST=emerge-rex coreboot Change-Id: Ie9c228ed7ccc83afaa8365f89c1d5cdedc4f0c8c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77006 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Copy devicetree from rex0Tyler Wang
Add initial devicetree config for karis. It's copied from rex0 and only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I89585a86e8afe636d3927a21a64451b59591acda Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-17mb/google/rex/var/karis: Copy Kconfig from rex0Tyler Wang
Add initial Kconfig settings for karis. Copied from rex for support audio codec, SD card and ISH. It's only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I4bcea7f5e678f2862b3477206838786ff5bad173 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77182 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Add TPM supportTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I4076ee4a16b7260db464760d5a19e1144081bab8 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77181 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Copy GPIO from rex0Tyler Wang
Add initial GPIO settings for karis. It's copied from rex0 and only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ic1e52a1eaca0aa5f68661826a70ccb89d6e302dc Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77003 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/ovis: Fix Bluetooth configurationJakub Czapiga
Bluetooth was missing USB configuration, so add it according to the schematics. BUG=b:290111789 TEST=Boot on Ovis and list bluetooth with `hciconfig` Change-Id: Iee8a3368bbad6c5b49f09ec7335d77ed63ecc784 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77146 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/skyrim: Enable SPL fusing on crystaldriftYunlong Jia
Enable Crystaldrift platform to send the fuse SPL (security patch level) command to the PSP. BUG=b:279499517 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1d41505e64bf54ad911ad7d287263013a9c458db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-08-16mb/google: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-16mb/google: Re-arrange mainboard_smi_sleep()Kyösti Mälkki
Change the order of enabling EC and GPE wake sources, so it comes more obvious we can use existing chromeec handlers without changes. Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74604 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/slippy: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I752d5644d6140e5a6d6f53543bbbc5ef7281f3b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74824 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/slippy: Re-arrange mainboard_smi_sleep()Kyösti Mälkki
Change-Id: I9ac7293e03bba773753f48163aca9385f819a71b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74822 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/auron: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I6b67358431d8c2b9f88b4e8948baf3497b902fed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74821 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16ACPI: Add usb_charge_mode_from_gnvs()Kyösti Mälkki
Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-16mb/google/nissa/var/pirrha: Update Kconfig for pirrhaSeunghwan Kim
Add support MIPI driver and DA7219 driver for pirrha. BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I6a8f0f942a54909627aad3bf447dc7225f57cef2 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-16mb/google/nissa/var/pirrha: Update DRIVER_TPM_I2C_BUS for pirrhaSeunghwan Kim
Correct TPM I2C BUS number for pirrha BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I9fa0b46db752d02368f19ce8c58a4122b371c100 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77164 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/nissa/var/pirrha: Increase VBT_DATA_SIZE_KB to 10Seunghwan Kim
Increase VBT_DATA_SIZE_KB to 10 since pirrha uses bigger VBT file. It includes MIPI power sequence data for panel. BUG=b:295112773 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: Ib6c293ccb4a8df3ebbd2271e7db2de4e7bd9cc3e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77163 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/nissa/var/pirrha: Update DQ/DQS tableSeunghwan Kim
BUG=b:292134655 BRANCH=nissa TEST=Boot to OS on pirrha ADV board Change-Id: I65429ec8d30b4458511f7c0138652528aadfde25 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76892 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-16mb/google/nissa/var/yaviks: Add elan i2c touchscreenWisley Chen
Implement support for elan i2c touchscreen and use fw_config to pick between i2c or HID-over-i2c touchscreen. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=build and verified touchscreen work Change-Id: I32ba97f5e5f6d280d1ae47da22360fde421a26c0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-15mb/google/beltino/smihandler: Remove 'return' from void functionElyes Haouas
Change-Id: Iadd8a0f3bae07918990cba8f33eb1e65f4e1977a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77188 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-15mb/google/dedede/var/boxy: update DPTF thermal settingsStanley Wu
Update DPTF thermal settings from thermal team suggestion: 1. Modify CPU passive policy to 95. 2. Modify TS0/TS1/TS2 passive policy to 90 for CPU. 3. Modify TS1 passtve policy watt to 6w. 4. Modify TS0/TS1/TS2 critical policy to 100. BUG=b:294479707 TEST=Build and verify DPTF value by thermal team on Boxy system Change-Id: Ic34e44f218ff980c54bf93841880fab5e21b3fca Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77108 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-13mb/google/nissa/var/yavilla: Adjust WLAN_PERST_L power sequenceTony Huang
With this change TPERST_HIGH could met spec. Before 160ms After 460ms(met spec min=400ms) BUG=b:295277868 TEST=emerge coreboot EE measured power sequence met spec boot to system and check wifi connection is fine Change-Id: Ifb909a55b36f2366132c3e20021c4bde4bc87a05 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-13mb/google/nissa/var/pirrha: Add GPIO tableSeunghwan Kim
Add GPIO table for pirrha based on pirrha ADV board schematics. BUG=b:292134655 TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I1f45365665b200fa97766344df2f9e06bc6dfb3d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76882 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11mb/starlabs/starbook: Add Raptor Lake StarBook Mk VI variantSean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7c92bf92ab4de546c3633fae7e19a302409508ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/74444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 11:08:16 +0000