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Generated 'build/dsdt.dsl' files are same.
Change-Id: I122f27bf7e7b809802efdbd443694b3d6e715108
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated 'build/dsdt.dsl' files are same.
Change-Id: I1cec4049adac74270641736709774156628b2539
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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We want to add some function declarations as static_testable to this
header but including it in a .c file outside of tests will yield a gcc
warning like:
error: 'function' declared 'static' but never defined
[-Werror=unused-function]
It seems these includes aren't necessary anyways so we just remove
them.
Change-Id: I17147136579140b94728ceb1c369b1348714bc53
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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We started depending on dsdt_top.asl in dsdt.asl but this newly added
board wasn't adapted yet, so have it catch up.
Change-Id: If00280a33fd9e5c3ef1b3d07c41e81ed18013714
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50021
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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lint-001-no-global-config-in-romstage error on
D0F0_PCIEXBAR_LO.
DOF0_PCIEXBAR_LO is defined in bootblock.c and
romstage.c.
Place D0F0_PCIEXBAR_XX in local gm35.h.
BUG = N/A
TEST = Build and boot QEMU x86 q35/ich9
Change-Id: Ia5ac9eb797de996186282193647313b9f7b42624
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
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Add wifi sar for galith
Using convertible mode of fw config to decide to load custom wifi sar or not.
BUG=b:176206495
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Cq-Depend: chromium:2649378,chrome-internal:3559387
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I0f9a7ddedef550317da4bf798317619ffd1fa979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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1. GPP_E5 => Remove unused GPIOs
2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO
Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ie802b540cea13000227c969bbc262f034d1b6b84
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Raise little CPU to 2GHz at romstage to improve boot time.
BUG=b:177389446
TEST=observe boot time by `cbmem`
Before: 1,062,359 us
After: 907,458 us
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I723a916d7f708627525ef11e3c5ea0b381f269aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Configuring GPP_G7 as NC causes SD card detection issue on sasuke.
So we'd like to remove the GPP_G7 override and keep the baseboard
configuration as native function (SDIO_WP).
BUG=b:175831709
BRANCH=firmware-dedede-13606.B
TEST=Built and verified SDR104 SD card operation on sasuke
Change-Id: If73337b482f04fd263caaa6fed0e54aa87bd876e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Except for one debug print in sarien, both functions are identical.
Move them to driver code to avoid unnecessary redundancy.
Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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BUG=b:178440482
TEST=emerge-asurada coreboot
BRANCH=none
Change-Id: Ica09b73f97509db065c93c6be757c0d77c9b7a87
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Generated 'build/dsdt.dsl' files are identical.
Change-Id: I9157d9fc61339792dbbc45e82e1cb04fa51c6aae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46077
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated 'build/dsdt.dsl' files are identical.
Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46163
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the GL9755 support to drobit and also fixes the S0ix can't into C3~C9 problem
BUG=b:174348200
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: I52df6b2cdebfaf8a5eb010c4af1a2cf3d918f5e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49921
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add variants overridetree.cb path remove unused registers
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2940332044aa4c2de6d58f5d0d2a2a7c1b2c3478
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Added device hid info to the MST RTD2141b device on
trembyle.
BRANCH=zork
BUG=b:147402710
TEST=Build and flash BIOS image, see 10EC2141 appears
under /sys/bus/i2c/devices
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: I97a67f9dbc31cd788d579252d7d355b24d97ca30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
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Tested with TianoCore payload (UefiPayloadPkg).
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics
- Internal microphone
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux and Windows
Not working:
- Discrete/Hybrid graphics
- Internal speakers
These two require new drivers to work correctly, which will be added and
enabled later.
Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With top-aligned bootblock this is no longer globally needed.
The default maximum is now a generous 256 KiB with couple
platforms having lower limits of 32 KiB and 64 KiB.
Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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CLKSRC6 for RP8 is free-running CLK hence ClkReq is not required.
TEST=Able to detect PCIe SD card over x1 slot.
Change-Id: I550d5be9cc7566708b0b86fcd1da833bc4bc828f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This patch adds the flash layout for shadowmountain.
BUG=b:175808146
TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I7073d9c783684051e33e7a33eca50007d286bb00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This reverts commit 2a1638a9cead257115ff82b18862d506015378b2.
The original commit broke Mandolin and with the revert applied, I can
boot into Linux via SeaBIOS again.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7024b6ff1e772bbc89f810c766655a5887ed8b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49950
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds mem_list_variant.txt that contains the only
memory parts used by brya0 for Proto-0 build and Makefile.inc
generated by gen_part_id.go using mem_list_variant.txt.
BUG=b:176491791
Change-Id: I3fe755564e7541a7abdfca0e5aa7fd786f5ca880
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
K4U6E3S4AA-MGCR
BUG=None
TEST=Build the sasukette board.
Change-Id: I57c9d22ae655032120f19add98ef454853428af5
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Already selected from SoC Kconfig.
Change-Id: I131f435ab0a30e33a70773a99c60284f8b9c82c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I7ba4625075fd3c27092d854903baf140521c8f7b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated 'build/dsdt.dsl' files are identical.
Change-Id: I8887b869e9ed809f7861b810c2fb994fa2ee062e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated 'build/dsdt.dsl' are identical.
Change-Id: I3a5ef0987f2e03e07f1de2b3b10d65dde3827c70
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated 'build/dsdt.dsl' are identical.
Change-Id: I856494c634c8c932faa7840b0fd0a35663f4de57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46157
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I07705aed2f41cd0d2a7f4b980046995f44395f07
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated 'build/dsdt.dsl' files are identical.
Change-Id: Ib07e4147f7f1b90f721be147d48ed12ae793c4fd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46159
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated 'build/dsdt.dsl' files are identical.
Change-Id: Iea2c0600d696f9da6774affdc33d9c50d5cf2c95
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I2ef51c0348e76cb34e118ed207de88cc753f8fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated 'Build/dsdt.dsl' are identical.
Change-Id: Ic01ca9b58fe948fe5ffbc9e80ea4bae91fb6d581
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated build/dsdt.dsl files are same.
Change-Id: Iaf26af76935dc8cd9642f047e833f0e8b14e6931
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated build/dsdt.dsl are identical.
Change-Id: I3cfa9d3a199a33ac8faddf4dbc1eed0df8703835
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated build/dsdt.dsl files are identical.
Change-Id: Id12c20dbe949c4badfe07578c6d202cd4cfb8191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46211
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated 'build/dsdt.dsl' files are identical.
Change-Id: I1ceb2abdd2562c145b01db7307d817c858d6b978
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Add memory DQ map based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If0bc153cd3a3391b1607848436f0ab5fcd54ce7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Per Facebook BIOS requirements 'Locator' field should not
have any space between words.
Tested=On OCP Delta Lake, dmidecode -t 17 to verify.
Change-Id: I2f6f1b2590c55d6da4ca32aef2f50eb332f441dc
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add camera ACPI configuration for Voema
BUG=b:169551066
TEST=Build and boot Voema. Start camera app and able to
capture images.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
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|
Set the supported C-State to C1 and C6. This matches the states in
CPUID(5).
Change-Id: If32b8256097b5b2bee7fb074fab105e4b54d14b3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49803
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Do not pass ACPI S3 state as a parameter, by locally
calling acpi_is_wakeup_s3() compiler has better chance
for optimizing HAVE_ACPI_RESUME=n case.
Test for acpi_s3_allowed() is already included in the
implementation of acpi_is_wakeup_s3() and is removed
as redunandant.
For ramstage, acpi_is_wakeup_s3() evaluates to
romstage_handoff_if_resume().
Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91424a45ae67186987630b7686102f467f57e7ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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This change uses the newly added meminit block driver and updates ADL
SoC and mainboard code accordingly.
BUG=b:172978729
Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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|
Change-Id: Ief0c3d36e6de6e18b7f2613f043ac4d31a193f9d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49249
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Unify the debug messages on raised SMIs.
Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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For board version 6 afterward, it will have external pull-up for
GPP_C12, and remove internal pull-up.
BUG=b:177618684
TEST=emerge-dedede coreboot, check evtest if SW_PEN_INSERTED event
(value:1/0) when insert/eject pen, and eject pen to wake system from s0ix
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I503873afb48384168dcd8a822c7246655898356e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
|
|
Declare the following panel for Katsu:
- BOE_TV105WUM_NW0
- STA_2081101QFH032011_53G
BUG=b:176523929
TEST=build Katsu image passed
BRANCH=kukui
Change-Id: I59a02198bc0e13f2760677ae4ea3eb05eb883464
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight
on and vary backlight.
BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was passed to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
needs to adjust the eDP phy setting to fix the eDP noise for WWAN.
DP_VS_LEVEL0_PREEMPH_LEVEL0, = 0x00 (0.4v 0db) swing 0, pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004B
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ibe720e26d2257e05a989eaa1fd85d542005cf6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48734
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Built google/auron (Lulu) provides identical 'dsdt.dsl' files.
Change-Id: I5728b220e88d4105fcf6e5cee78662bc80fa01d7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: Iab19538e1f5a74b714cb2a34855d9717315b9018
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Change-Id: Ib184dbfef05608bbf18d49fee5cbc9dd12ed6751
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49883
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Boten customized SAR table.
BUG=b:175931508
BRANCH=dedede
TEST=build and test no Boten
Change-Id: I3b00f56c8b890979cbf2155c97a3a064d8b0ba1a
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
BUG=b:177288782
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: I98f741da4a22494883939c4efe7960c66e71c6a7
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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"usb2_ports[7]" for internal bluetooth device was configured as
'USB2_PORT_EMPTY' mistakenly in previous patch, so we need to enable
it again.
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=Built and verified BT device existence with lsusb
Change-Id: Id2900152e23bbc2f454d064dc86a9e45e934ea0f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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This patch adds explicit initializations for the remaining named display
(power) control GPIOs to the bootblock GPIO init code. These pins are
usually mapped to pins that are already configured to pull-downs on
power-on reset so this wasn't really required, but we have already moved
them around so often that you never know when EEs might one day move
them to a pin with a different power-on reset configuration, so it's
better to be explicit.
In one particular case, GPIO(67) (used by CoachZ rev1+ but not by
anything else for the EN_PP3300_DX_EDP pin) is not actually a pull-down
on boot, even though that is claimed by the datasheet. This is likely
due to the fact that it can serve as the SPI_HOLD pin for the boot flash
QSPI bus, so even though our board's boot flash doesn't really use that
pin, it seems that the boot ROM still configures it as such.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I533baa962d2dfc87cfa510f442ed2e8912e0e5b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: mturney mturney <mturney@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
|
|
This conflicts with the MSTH i2c_tunnel.
BUG=b:175146875
BRANCH=zork
TEST=Boot trembyle and inspect ACPI tables.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iac04c7dc361d427f5ebb99644aa70bd0c7dbb918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
It's easier to understand what these symbolic names mean rather than
using the constants; the static.c will will end up (indirectly)
including `soc/usb.h` therefore the macros are in scope here.
Change-Id: I5ef977a05a2522e177f32c99bfab74f9288ae869
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: Ib31c5d55e30b958d3e552e8d0b4a160947444636
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are:
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:165209698
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: I80afd6bf1257b9a72d0d7651b48d243ebaf5de2f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
The only difference is an additional include that is no longer needed.
Change-Id: I0053d03aa4d05f5c0fa833d8634419b6667e38a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49832
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There's no need to repeat the same code on every board.
Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change uses the newly added meminit block driver and updates TGL
SoC and mainboard code accordingly.
TEST=Verified that UPDs are configured correctly with and without this
change.
Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
ARCH_X86 is already selected.
Change-Id: I2be69e0b7a1889794121ed94380e543ac420218b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Generated 'build/dsdt.dsl' are identical.
Change-Id: I4f8b77b3f196ca51346bb7932a40875c4dd5d2a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Generated build/dsdt.dsl are same.
Change-Id: I9c7cbc4ee874657a7381b1b220872c4ebecd0821
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46085
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Built for packardbell/ms2290 provides same build/dsdt.dsl file.
Change-Id: I5f1dbb2595c3ee8cb35bb8a6431288f4a96ce978
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Built provides same dsdt.dsl file for lippert/frontrunner-af
Change-Id: I61d8af98e2003547e332f463b23c1e1cf79f7f00
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I18667ae74454e0db83fb40d8f130909510ddc379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I9764d90e713f35d54056fbafae3e3ada18bea1eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I3bee00030f03577b0449202233f7e76f7de96339
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I95eab372b3c6b6df5231f0d232e878576bab5290
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: Ice7cfc263c339ba9ec3705c1cee44a6d69f2e4d3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I91e25fe62080582b925fa1f1a88512f318ab9415
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I2825dff6b68da9b1e2bb13f03a4251af02438b66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: Id4a724193c4c120373a3e696ebd1fb7155fd8531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I6e928c23165abad623ee3c2a26e090b029d55572
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I9d0e4982888823bb62a174a603a126676e68e308
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I56f844706ba6bde3e57a6a81ff1d8e16863913f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I3890f75e3c27a689e9d57b4708514160e1550fdb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I5859c64b0ccd1dfdce040b2c3bbdd9192617ffbe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Generated 'build/dsdt.dsl' are identical.
Change-Id: I305561625d973093645236c77ef13a96ab780f94
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I4c5c67d70e004eeece61e66d427d6f9df9cab4ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
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Generated 'build/dsdt.dsl' files are identical.
Change-Id: I3b553e1b68ee8f236fcab311a076001b94a47975
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46204
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated 'build/dsdt.dsl' are identical.
Change-Id: I0767afcb0ffdd6f9a8d83209955d42d9e89325e9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated 'dsdt.dsl' files are identical.
Change-Id: Ifdd5008bcb9c7e41e637a30f70316c7926f927b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: If46ef5ffbd3de82d793a095b011e5740b776ff14
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ifa30e9d2a71eae9a438e84367fd8b4f8bd920983
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I75f534245d37f401357b611efc5c190e8a872d02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I4e6d5048ca9e949a70f3619f05b74870c1f1fe30
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Generated 'build/dsdt.dsl' are identical.
Change-Id: I8843d418bd9c34a4f079444bc6ce8ecd4559e36d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All Broadwell boards only use the `mainboard_pre_raminit` function to
call `mainboard_fill_pei_data` and optionally `mainboard_fill_spd_data`.
Move the declaration and weak definition of `mainboard_fill_spd_data` to
platform code, replace the call to `mainboard_pre_raminit` in romstage.c
with calls to `mainboard_fill_pei_data` and `mainboard_fill_spd_data`,
and delete all other instances of `mainboard_pre_raminit` for Broadwell.
Finally, delete now-empty romstage.c and spd.h files from mainboards.
Change-Id: I3334b20bd7138bb753b996a137ff106e87c6e8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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