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2022-06-13mb/google/dedede/beadrix: Update SoC gpio pin of I2C cameraTeddy Shih
Update SoC GPIO setting of unused I2C camera pins according to beadrix schematics. GPP_H6 : NF1 -> NC (AP_I2C_CAM_SDA) GPP_H7 : NF1 -> NC (AP_I2C_CAM_SCL) BRANCH=dedede BUG=b:235005592 TEST=on beadrix, validated by beadrix's camera still working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I8be57406a44096c764c1faa8f45267d08c4694fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/64971 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/google/dedede/beadrix: Update probe daughter LTE mainboard SARTeddy Shih
Update FW_CONFIG probe for daughter board LTE and mainboard SAR according to beadrix schematics. BRANCH=dedede BUG=b:226910787, b:213549229, b:233983127 TEST=on beadrix, validated by beadrix LTE working properly. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I126a1c548b6314acc0749fcfbdffd8f482c4f46c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-12mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByteFelix Held
The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so it won't fit in the flash and makes soc_update_apob_cache return early before writing the APOB data from DRAM into the flash with this warning: [WARN ] RAM APOB data is too large 1db18 > 18000 Increasing the RW_MRC_CACHE size to 120 kByte fixes this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/google/corsola: Fix PS8640 power-on T6 sequenceRuihai Zhou
The T6 of PS8640 power on sequence should be larger than 0ms, but it's -0.062ms now. Add 100us delay between VRF12 and VCN33. The PS8640 power-on sequence is described in the "PS8640_DS_V1.4_20200210.docx". BUG=b:235448279 BRANCH=None TEST=The sequence T6 is larger than 0ms when power on. Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I0b8a37d6119dc027a9d1c0a62c087b0a7ef14cac Reviewed-on: https://review.coreboot.org/c/coreboot/+/65084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-10mb/google/brya/variants/felwinter: Enable TBT PCIe Root Port 0John Su
The TBT device can't be recognized after we re-plug it at DB type-c port. Intel found that tbt_pcie_rp0 has mapping error after each re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this problem and take this as short term solution. Intel will implement re-mapping mechanism in ACPI for long term solution. BUG=b:230141802 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I61429033dfe64d67916167bb901bdd8246db953e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10mb/intel/adlrvp: Add 5G WWAN ACPI support for adlrvp_rpl_ext_ecCliff Huang
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3 are generated under the root port. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I74434d833086f639927d8369f8a6e3af31dd99e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64648 Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/google/brya: Select SOC_INTEL_RAPTORLAKE for skolas variantsBora Guvendik
BUG=b:229134437 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib0531ff736ed7ac52bff8607b26b3e7f1d3ac3ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/intel/adlrvp: Select SOC_INTEL_RAPTORLAKE adlrvp_rpl_ext_ec variantBora Guvendik
BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I12eab0fe2a3c21011f50c72718514fbc90cbe658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-10mb/chausie/ec: Set MS bit in SW02Fred Reitberger
Set the MS bit in EC SW02 register to enable s0i3 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I97b6adf48b49635251c70015f1d87fd8ca11d539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-10mb/google/brask/variants/moli: correct ddi_ports_configRaihow Shi
1. enable DDI_PORT_1, DDI_PORT_3 hot plug detection to let tcp0 and tcp2 can display 2. remove DDI_ENABLE_DDC for Port 2, because tcp-dp dosen't need to enable DDC BUG=b:234521799 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1354b82d881ebd838c310b32ae28ac2628ab8c9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/google/brask/variants/moli: enable USB retimerRaihow Shi
Enable USB retimer in moli overridetree. BUG=b:233869074 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ib7ea0b0d85776857d07e129935059397720fa0e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10mb/intel/adlrvp: disable unused root port 1, 3, 4 for Adl-P RVPCliff Huang
In Adl-P RVP, those interfaces are used as USB ports. BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I322280ab02361e3a2a5925d69f33b23453d36dbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63946 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVPCliff Huang
Use clock src and clock req to 7 for x4 slot. Remove free running clock setting for clock 6. Configure gpio for source clock OEB native function going to x4 slot. BUG=b:233252409 BRANCH=firmware-brya-14505.B TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check the device. ex: 58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01) NOTE: The bus number varies. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-06-09mb/starlabs/lite: Disable Burst in Power Saver profileSean Rhodes
When the CMOS option `power_profile` is set to Power Saver, disable Burst. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-06-09mb/google/dedede/var/shotzo: Deselect BASEBOARD_DEDEDE_LAPTOPTony Huang
Shotzo is not a laptop (it is a Chromebase), therefore deselect BASEBOARD_DEDEDE_LAPTOP. BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: I4669ef163e4bd8f2de556a051197802ee2d54927 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65015 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/dedede: Create shotzo variantTony Huang
Create the shotzo variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=b:235303242 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SHOTZO Change-Id: Ia3dc9ea6d1b369b54a966ad86f1531305b8a7f57 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65014 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2022-06-09mb/google/brask/variants/moli: remove mainboard_vbt_filename in ramstageRaihow Shi
mainboard_vbt_filename() is to decide which VBT to return, but moli only has one VBT, so it doesn't need this function. BUG=b:234521809 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia9c1495c8cb7bf7b47d9c616891a791a32b9d805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64848 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/brya: Create ghost4adl variantJack Rosenthal
Create new variant of Brya "ghost4adl". Memory config and device tree was sourced from the schematics (revision 7670d041f40279b5126990f20ec8f90c0538440c). GPIO overrides have not been added yet. This is to be added in a follow-on CL. BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-06-09mb/google/brya/var/agah: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 portIvy Jian
Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`. The change is required to detect USB2 device on type-C port of Agah boards. BUG=b:233554817 TEST=build and test USB2 hub could be detected on both the Type-C ports. ================================================================= usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00 usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0 usb 3-3: Product: USB 2.0 Hub hub 3-3:1.0: USB hub found hub 3-3:1.0: 4 ports detected ================================================================= Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/nissa/var/craask: Generate SPD ID for supported memory partTyler Wang
Add craaskbowl supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3LKBKB0BM-MGCP 2. Hynix H9JCNNNCP3MLYR-N6E BUG=b:235134420 TEST=Use part_id_gen to generate related settings Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64858 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/google/brya: Add memory parts for CrotaTerry Chen
Add a mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 1 (0001) H9JCNNNCP3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 2 (0010) K3LKLKL0EM-MGCN 3 (0011) H58G56AK6BX069 2 (0010) BUG=b:233830713 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: If9f2b65717a05576fa6b4fb1f53133902ff1a7c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64982 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-09mb/qemu-armv7: Initialize cbmemArthur Heymans
Change-Id: I607205a0d44c71eb26031ced7a8af303efacd6f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-09mb/aopen/dxplplusu/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: Iae3343e66906a8123b3d8de2b67948f286e4ad32 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I63b8b8a086e2c5ede765855b3c803206edf87690 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/kahlee: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: I19835510b89cd243277f0c9701209c81bdf6ea29 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/cyan: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Ib8719143a5a217173b34931e9c0ef02e9895d0a5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: Id61c537cc91edbd407fb6429eb4dd2bc8bc7f123 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Idc24216209bbfe73ef4197d4b8101f0d7e5891f7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I5c16893b9c98f36fd2c210ed301c2ebb65f95368 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/kahlee/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: Id7975a8cad4078a523de2466919982ad540f5dd3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/slippy/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I61ef7b53e851f4c2367cba43ff76b200e9490ad2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/aopen/dxplplusu/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: If482b2ad4ba7d4ed1ca8c0695690ede153ed1e2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-09mb/google/jecht/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreaterEqual(a, b)` with `a >= b`. Change-Id: I56e8fdb2503a84ded2bcf183402602579c3f2997 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-08mb/google/brya/var/banshee: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C3 | | C0 C2 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerge-brya coreboot BRANCH=firmware-brya-14505.B Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I2153f826d7ff05f42935f08d5d1f5127ac944575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64728 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08mb/google/brya/var/brask: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. C2 C0 A3 A2 +----------------+ | REAR | | | | | | | | FRONT | +----------------+ C1 A1 A0 BUG=b:232298007 TEST=emerge-brya coreboot BRANCH=firmware-brya-14505.B Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I6a9ead24ef9d73bc0b09301cf641009ced0c6810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64732 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08mb/google/corsola: Correct EC-is-trusted logicYu-Ping Wu
With Cr50, the GPIO EC_IN_RW_ODL is used to determine whether EC is trusted. However, with Ti50 where corsola has been switched to, it is determined by Ti50's boot mode. If the boot mode is TRUSTED_RO, the VB2_CONTEXT_EC_TRUSTED flag will be set in check_boot_mode(). Therefore in the Ti50 case get_ec_is_trusted() can just return 0. The current code of get_ec_is_trusted() only checks the GPIO, which causes the EC to be always considered "trusted". Therefore, correct the return value to 0 for TPM_GOOGLE_TI50. BUG=b:235053870 TEST=emerge-corsola coreboot TEST=firmware-DevMode passed in kingler (with Ti50) BRANCH=none Change-Id: I59b16238bfb487832ef618668c0f9addc1ee7937 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64998 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-08mb/google/brask/var/kuldax: add fw_config and enable BT offloadDavid Wu
add fw_config probe for auido and enable BT offload support. BUG=b:232419816 b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08mb/google/brask/var/kuldax: Update overridetreeDavid Wu
Update override devicetree based on schematics. BUG=b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08mb/google/brask/var/kuldax: Update gpio tableDavid Wu
Based on latest schematic to update the gpio table. BUG=b:232419765 TEST=FW_NAME=kuldax emerge-brask coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-08mb/google/brya/var/redrix: Configure camera EEPROM power always onArec Kao
Remove EEPROM power source interconnect with camera power on/off and keep it always on. There appears to be a rare case where the camera EEPROM is not able to be read from. As a workaround, this patch leaves the EEPROM power rail on in S0. BUG=b:229049914 TEST=tested the changes with redrix 5MP(ov5675/hi556) camera. Change-Id: I9efab9bb65632a73c1c2635729c38a2aa14c69b2 Signed-off-by: Arec Kao <arec.kao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-08mb/google/brya: Add GPS _DSM subfunction support for Nvidia GPUTim Wawrzynczak
The _DSM subfunction for the Nvidia GN20 supports 1 additional subfunction, known as GPS, which is required to support GPU Boost. This implementation is minimal, essentially letting the GPU manage its own temperature. BUG=b:214581372 TEST=abuild Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08mb/google/brya/var/agah: Fix ACPI power sequencingTim Wawrzynczak
Now that the power sequencing for the GPU is in a better shape, ensure that the ACPI code that performs power sequencing matches the C code that does the same. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08mb/google/brya/var/agah: Add delays to GPU power off sequenceTim Wawrzynczak
During the GPU power down sequence, each power rail should reach below at least 10% before the next rail is sequenced down; based on scope shots for a board, conservative delays between each rail are added; they will likely be more fine-tuned later on. BUG=b:233959099 TEST=sequence verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I28ada3a01b86996e9c7802f8bd18b9acda6bb343 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-08mb/google/corsola: Enable ps8640 for steelixZanxi Chen
Currently, the display does not work in steelix. Steelix uses ps8640 eDP bridge IC, which is different from its reference board kingler. So we should enable ps8640 for steelix. BUG=b:232195941 TEST=firmware bootsplash is shown on eDP panel of steelix. Change-Id: I8c6310794c89fc8aa0e69e114c1f7ebd5479c549 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-07mb/google/nissa/var/craask: Add MIPI camera settingsTyler Wang
Add OVTI8856 information for craask BUG=b:232656913 TEST=Build and boot on craask Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ice490f31e9ab8fffff6a7a5d24f769efea91188d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-07mb/google/brya/var/vell: Add new LP5 RAM IDShon
Add the support LP5 RAM parts for vell: DRAM Part Name ID to assign Vendor H58G56AK6BX069 2 (0010) Hynix BUG=b:227595062 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: Ibe09285c15b28ceeb6ab0d6c94f90e00584ac07d Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-07Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki
With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07mb/intel/adlrvp: Add VBT for adlrvp with Raptor Lake siliconBora Guvendik
Board id is same so use cpuid to decide to use ADL or RPL VBT. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Change-Id: I954c228f82110c3e7c8474e47cabab8220ff19b9 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64672 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-07mb/intel/adlrvp: Add initial code for adlrvp with raptorlake siliconBora Guvendik
Take adlrvp_p as a baseline code and add a new variant of ADL RVP with Raptor Lake silicon. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I880abe0f300118f461523173cc0d50a2fbc99e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07mb/google/guybrush: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232298307 TEST=None Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ic9c45aebaf02a16b755f4731e1e3b46cd5dec829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07mb/google/skyrim: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | | | +----------------+ BUG=b:232298017 TEST=None Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Idca3dd468f1b9fde37a1bbf20d65768032c7160b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-07mb/intel/ehlcrb: Store vboot VBNV in SPI flashLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I0d609f0db475877d0ef1f47ab89c34dccb6e16d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-07mb/intel/ehlcrb: Update vboot kconfig selectionsLean Sheng Tan
Since many vboot settings are heavily tuned for Chrome OS support, use these vboot kconfigs for the non Chrome OS use case and tune for EHL CRB vboot support. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ie1ffd4973fb18bbca5c5b9c888a4dd0e662b1574 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-06-07mb/google/skyrim/var/skyrim: Add audio codec and amp supportIan Feng
Add two combination: 1. ALC5682I-VS and ALC1019 2. NAU88L25 and MAX98360 BUG=b:227165780, b:228879074 TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I36d7b5c4e88825ceaa6922d9e3bed366f55a0d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07mb/google/guybrush: Remove TODO's and update textJon Murphy
Remove TODO's for dummy DXIO descriptors, update comment to reflect what they are. These devices are needed for the platform to function properly. Also remove the TODO for DDI descriptors as they are functioning correctly. BUG=b:232952508 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I1535c08cac3f0bcb30061aba2aa593eb22109387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-06mb/google/brya/acpi: Add support for NVPCF _DSM subfunctionTim Wawrzynczak
The Nvidia GPU kernel driver supports another _DSM subfunction which is known as NVPCF (Nvidia Platform and Control Framework). The subfunction informs the kernel driver about Dynamic Boost parameters, which is done at init time, but can also be changed dynamically. BUG=b:214581372 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-06mb/google/brya/var/kinox: Set power limit based on charger typeDtrain Hsu
Set different power limit values using host command to detect charger type from ec. Scenario: 1. With 90W customized adapter, set to baseline. 2. With 170W customized adapter, set to performance. 3. With above 90W barrel jack/type-c adapter, set to performance. 4. With below 90W barrel jack/type-c adapter, set to baseline. BUG=b:231911918 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I9c8a5a7de8249e61468e277ec55348b660253c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-06-05mb/prodrive/atlas: Increase CBFS size to 8MBLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05mb/prodrive/atlas: Add data.vbt for 4 DPs supportLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-05mb/google/octopus: Demote NHLT log messages from error to infoMatt DeVillier
Change-Id: Ib2d0c6a23b66e6e61cc8ea09a443e19a4b37c66d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-05mb/prodrive/atlas: Update pcie config for i225Lean Sheng Tan
Enable clk 1, LTR & AER for PCIe-to-i225 bridge. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Fix FSP debug boot hangLean Sheng Tan
When device tcss_xhci is disabled, boot hang occurs at FSP-S TcssInit(): "IomReadyCheck Failed!" Enabling this device fixes the issue. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ie001bd56b403d511c397737fbc214ed64956910d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64901 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-05mb/prodrive/atlas: Add display configs for 4 DisplayPortsLean Sheng Tan
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iea5312055305bc3354755607a7bfafa7980c6d21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-06-05mb/google/brya/var/kinox: Update gpio configurationDtrain Hsu
Follow GPIO_Table_0527.xlsx to update gpio configuration. - Set GPP_A15 to NC. - Set GPP_A20 to TCP_DP1_HPD (native function1). BUG=b:225384873 TEST=Build and boot to Chrome OS. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-06-03mb/google/brya/var/mithrax: Update DPTF parameters for MithraxJohn Su
Follow thermal table from thermal team. Chang list: 1. Update TEMP_PCT of Active Policy for TSR1. BUG=b:230829301 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-03mb/google/brya/variants/nereid: Add DPTF passive and critical policies for ↵Vidya Gopalakrishnan
Nereid BUG=b:233030505 BRANCH=None TEST=Build FW and test on Nereid board. Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: I195f4b507ee57948751f0119735d8350dfce984b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
2022-06-03mb/google/nissa/craask: Configure the external V1p05/Vnn/VnnSxTyler Wang
This patch configures external V1p05/Vnn/VnnSx rails for Craask to achieve the better power savings. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:233717182 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-03mb/google/nissa/var/nivviks: Enable ISH when UFS is presentReka Norman
In order to enable the UFS controller (PCI device 12.7), the PCI specification says that the device at function 0 in the same slot must also be enabled, which is the ISH. Therefore, enable ISH when UFS is present. For more context on why this is necessary, see CB:62662 which enabled UFS and ISH for adlrvp_n. BUG=b:234136500 TEST=Build test. Will test that UFS works once we have hardware. Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Daniil Lunev <dlunev@chromium.org>
2022-06-02mb/purism/librem_mini: Hide Linux GPIO LED from WindowsMatt DeVillier
Hide the Linux gpio-led ACPI device from Windows by setting the device status (_STA) to 0xB (enabled, hidden) so Windows doesn't show an unknown device/missing drivers in Device Manger. Linux doesn't care about the _STA value. Test: build/boot Windows (10/11) and Linux (PureOS 10) on a Librem Mini v2, verify LED works under Linux, is ignored under Windows Change-Id: If3ee0db685a2f7dab505602afa98c3c2d5adf5d3 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-02mb/google/brya: Add new skolas baseboardNick Vaccaro
This commit adds the skolas baseboard, which is basically the brya baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder Lake SoC. This commit also adds the skolas baseboard variant skolas4es. Since this baseboard is identical to the brya baseboard with the exception of the SoC used, the new baseboard and the new baseboard's first variant will be a copy of the current brya baseboard and brya0 variant. For now, the skolas baseboard and skolas4es variant will continue to use ADL-P. This allows for two benefits: 1. software to be proven out on existing hardware prior to RPL SoC support landing, and 2. allows us not to have to wait for RPL SoC changes prior to getting the mainboard changes in place Once the RPL SoC code has merged, I will update the skolas baseboard and skolas4es variant to use RPL instead of ADL. BUG=b:229134437 TEST=util/abuild/abuild -p none -t google/brya -x -a -c max Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-06-02mb/google/brya/variants/osiris: Remove KB_MT from overridetreeDavid Wu
All Osiris SKUs use the new RGB gaming keyboard, so don't need the fw_config to decide keyboard matrix. BUG=b:220800586 TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I19211c345de0b315d65ec64efc70826e81315810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-06-02mb/intel/adlrvp: Enable DPTF for ADL-N RVPVidya Gopalakrishnan
BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy. Verified fan control successfully when participant reaches temp threshold as per Active Policy. Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy. Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Icafacfca6a026ec3b42906790831f11fd2f1b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-06-02mb/intel/adlrvp: Set power limits dynamically for ADL-N SKUsVidya Gopalakrishnan
This patch adds support for the ADL-N SKUs based on the PCH ID. Document reference: 645548 (ADL-N EDS Volume 1). BUG=None BRANCH=None TEST=Build FW and test on adln_rvp board Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Change-Id: Ie49398b8a7de8d8cff3536eae6a5e893980f9c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-06-02mb/google/nissa/var/craask: Disable PCIe WLAN pinsTyler Wang
Craask uses CNVi WLAN, so disable the PCIe-related GPIOs. BUG=b:229040345 Test=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I7bcf041503dcee448758dac46b1c9711d0b02ba3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-01mb/lenovo/w541/Kconfig: sort alphabeticallyPeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9cefa29738b42dd08cb00489ad6e8644e3fc405e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/t440p/Kconfig: remove duplicates and sort alphabeticallyPeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I47fded50377ab624e4bceb320a5e069a7f36c2fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/t440p/hda_verb: WhitespacePeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I92c167bf95e605e098324b9e80cfaab8f589dcab Reviewed-on: https://review.coreboot.org/c/coreboot/+/63995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/w541/hda_verb: WhitespacePeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I284a5e39ca4b0032ed0c8e3a92c095db319d1691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/w541/dsdt.asl: Remove redundant commentFelix Singer
Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: Ide938a40ed1f6869ee248ed46f6bf29f95649490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/lenovo/t440p/cmos: Remove unused optionsPeter Lemenkov
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: I9bf95ed74468e283bab79a5f25aee758d37d926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/google/brya/var/agah: Enable EC keyboard backlightTony Huang
BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I90d9f2e298e54832bc077eae1c8be0e39c151d90 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-06-01mb/google/brya/var/kinox: Set memory SMBus addresses based on board revDtrain Hsu
Starting with id 2, boards switched the memory SMBus slave address, and use 0x50, 0x52. BUG=b:233975373 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I5e683ffdbc0727259ee796610cd97a6e378bf335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-01mb/google/corsola: Add new board 'steelix'Zanxi Chen
Add a new kingler follower 'steelix'. BUG=b:232195941 TEST=make # select steelix Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-01mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEGArthur Heymans
Tested with SMI_DEBUG: SMM prints things on the console. Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-01mb/google/brya/var/craask: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia288937ef3a4229088b60d87d31ea88057377a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-01mb/google/brya/var/nivviks: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: If2a77c0239646759e0192b72ba1991d334dd15aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-01mb/google/brya/var/nereid: Add ACPI _PLD custom valuesWon Chung
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I47b069377046652ba4d278733a15bbca98bdb739 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-06-01mb/google/brya/var/kinox: Add delay time for BH799BB rtd3Dtrain Hsu
This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence. We checked power on sequence requires enable pin prior to reset pin delay of 50ms and add delay of 20ms to meet the sequence on various eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:232327947 TEST=Build and suspend_stress_test -c 2500 pass Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-01mb/google/dedede/beadrix: Add fw_config probe for ALC5682-VD & VSTeddy Shih
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BRANCH=dedede BUG=b:226910787,b:232057623 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I059b750743ab3b29d17c50d0d4301fbae4873acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2022-06-01sc7280: Improve performance by removing delays in cpucp initSudheer Kumar Amrabadi
As cpucp prepare takes 300 msec moving to before ramstage BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board observed total timestamp as 1.73 sec from 1.97 sec Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-05-31mb/starlabs/lite/glk: Don't configure GPIO's 147 through 156Sean Rhodes
These are configured by the TXE, so they do not need to be configured. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia1bf4e32aa156a0e1a74df2f62eb31cdadb376a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/glk: Simplify GPIO macrosSean Rhodes
Use shorter macros to configure GPIOs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I91961658dca0902080576134e63e6d8a7c78d711 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/starlabs/lite/glk: Disconnect unused GPIOsSean Rhodes
Disconnect GPIOs that are unused or not connected. Also, update comments that are vague or have errors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic83797b8a8e05eed99db0356f360a329f6fbf347 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-31mb/google/nissa/var/craask: Generate SPD ID for supported memory partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. K3LKLKL0EM-MGCN BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ie022dd95929549ddd403d4c1d1c52174fd3fd721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-31mb/google/brya/var/kinox: Select VBT based on FW_CONFIGDtrain Hsu
Select vbt bin files based on DB_DISPLAY field of FW_CONFIG. BUG=b:233690293 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Idb92be66927259732bfd27e4db2c9f242da7d200 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-05-31mb/google/brya/var/taniks: Modify DPA value to 100 for taniksLeo Chou
In order to meet the OEM's acoustic specifications, the pre-wake randomization time (DPA) is set to 100. BUG=b:228410327 TEST=build FW and checked DPA value by fsp log. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Idaf3f931a2c0f2373445948e5f53a82328ec7ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-31mb/google/nissa: Add and default to 16 MB layoutKangheui Won
Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and make it default for nissa. BUG=b:202783191 TEST=build nissa and brya firmware, check they're still 32MB Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-31mb/lenovo: Rename t440p to haswellFelix Singer
In preparation to follow-up commits, rename the mainboard folder from t440p to haswell, which will have more variants later. Change-Id: I4a9d68d54d5f0821bbf85faaa620855d456c97f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-05-31mb/starlabs/lite/{glk/glkr}: Configure prt0_gpioSean Rhodes
PERST_0 is not used, so set this to GPIO_PRT0_UDEF (undefined) to ensure that an undefined address is not added to GNVS. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac9b116b2fa28824a89db28911188364dc9a1a53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-30mb/asrock/h81m-hds: Reorder selects alphabeticallyFelix Singer
Change-Id: I18398efefcb4171496c39462c23514ad61659213 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>