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2020-11-10mb/hp: Add HP EliteBook Folio 9480mIru Cai
The code is based on autoport, with necessary modifications. This laptop uses SMSC MEC1322 embedded controller, but the EC interface is the same as the EliteBook laptops of previous generations that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need EC firmware inserted into CBFS. We also need to leave the end of the OEM flash content untouched, so the default ROM size is set to 12MiB instead of 16MiB, and we need to modify the IFD when flashing. Thanks to persmule for providing the laptop and pointing out how to program the system flash chip of it. Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-10mb/google/puff/var/dooly: Add WEIDA touchscreen deviceTony Huang
Adds ACPI properties for WDT8762A device. Per spec v0.8 HID name WDHT2002 T14=100ms BUG=b:163561649 BRANCH=puff TEST=emerge-puff coreboot and check system dmesg and evtest can get device. Change-Id: I178e9d5aa1e1501d33b3cd4092f3f522bb6f1a74 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-11-09soc/intel/skylake: Enable PCH thermal depending on devicetreeBenjamin Doron
Hook up PCH thermal subsystem configuration to devicetree. Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-09mb/emulation/q35: Define pm_acpi_smi_cmd_portArthur Heymans
The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port. This will be used by the common save state handler. Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45814 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09mb/intel/adlrvp: Replace if-else-if ladder with switch constructSridhar Siricilla
The patch replaces if-else-if ladder with switch case for readability purpose. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47054 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09hatch: Create genesis variantMatt Ziegelbaum
Create the genesis variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:172620124 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_GENESIS Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org> Change-Id: I70886c2c5a25f5de1a4941ff235547ee812fa50d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-11-09mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvpV Sowmya
This patch adds the PMC MUX and CONx devices for adlrvp. Device specific method contains the port and orientation details used to configure the mux. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects in SSDT tables. Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-09mb/purism/librem_cnl: Add new variant 'Librem Mini v2'Matt DeVillier
Add Kconfig entries, and update existing documentation to accomodate both v1/v2 versions of the board. Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09mb/purism/librem_mini: Fix USB_OC mapping in devicetreeMatt DeVillier
Correct USB over-current mappings in devicetree now that the GPIO config has been fixed per schematics. Change-Id: I564630231933c7c17a2c0a2a403fdcca9189b92e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-09mb/purism/librem_mini: drop PcieRpSlotImplemented from LAN PCIeMatt DeVillier
The LAN NIC is onboard, not installed in a slot. Change-Id: I77ee7ee8c944b7942ca78d35cd881277c4030ab9 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLANMatt DeVillier
Add strings for M.2 keying and number of PCIe lanes. Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09mb/purism/librem_mini: Fix PCIe clock source mapping in devicetreeMatt DeVillier
Correct PCIe clock source mapping in devicetree now that the GPIO config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers under their associated PCIe root ports. Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-09mb/purism/librem_mini: Adjust GPIO pad config per schematicsMatt DeVillier
- set pads GPP_B6/B8 for PCIe CLK_REQ lines - set pad GPP_B14 to speaker output - adjust comment for GPP_C22 / USB3_P1_PWREN - set pad GPP_E4 to NF1 / SATA_DEVSLP0 - set pads GPP_E9/E10 to USB2_OC0#/USB2_OC1# Change-Id: I8bf8af620370ec2d4c864e513db5d710a9c65d27 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47220 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09mb/google/volteer/eldrid: Describe the privacy_gpioRicardo Ribalda
Add information regarding the privacy pin on the overridetree and the gpio. BUG=b:171888751 Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/hatch/jinlon: Describe the privacy_gpioRicardo Ribalda
Add information regarding the privacy pin on the overridetree and gpio. BUG=b:169840271 Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/dedede/variants/magolor: Update Power Limit2 minimum valueSumeet R Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value for magolor board. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=b:168353037 BRANCH=None TEST=Build and test on magolor board Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09mb/google/dedede/var/boten: Add LTE power on/off sequenceKarthikeyan Ramasubramanian
LTE module used in boten has a specific power on/off sequence. GPIOs related to power sequnce are: * GPP_A10 - LTE_PWR_OFF_R_ODL * GPP_H17 - LTE_RESET_R_ODL 1. Power on: GPP_A10 -> 20ms -> GPP_H17 2. Power off: GPP_H17 -> 10ms -> GPP_A10 3. Warm reset: Power off -> 500ms -> Power on Configure the GPIOs based on these requirements. BUG=b:163100335 TEST=Build and boot Boten to OS. Ensure that the LTE module power sequence requirements are met. Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/dedede: Add support for variant specific SMI sleep flowKarthikeyan Ramasubramanian
This support is required to power off certain components that exist only in certain variants. BUG=None TEST=Build and boot Boten to OS. Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/volteer/var/voema: Add memory parts and generate DRAM IDsDavid Wu
This change adds memory parts used by variant voema to mem_parts_used.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:171755775 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09Atlas: Wake up AP on AC plug and unplugDaisuke Nojiri
This patch makes Atlas resume from S0ix by AC plug and unplug. BUG=b:165328935 BRANCH=atlas TEST=Put Atlas in suspend. Wake it up by AC plug. TEST=Put Atlas in suspend. Wake it up by AC unplug. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09mb/google/dedede/var/drawcia: Remove camera EEPROM power resourceKarthikeyan Ramasubramanian
EEPROM in the camera module does not require any specific power resources. This will ensure that no unnecessary resources are turned on while accessing the camera EEPROM. BUG=b:167938257 TEST=Build and boot to OS in Drawlat. Ensure that the camera EEPROM is listed in the output of i2cdetect. Change-Id: Iece9b3f657bf94a21cc08bf1745353575858f9b2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/dedede: Enable Wake on AC connect and disconnectKarthikeyan Ramasubramanian
Handle AC connect and disconnect notifications from Embedded Controller (EC) and wake from S3/S0ix. BUG=b:172266344 TEST=Build and Boot to OS in Drawlat. Ensure that the system wakes up from suspend on AC connect and disconnect on both the TypeC ports. 276 | 2020-11-04 12:21:29 | S0ix Enter 277 | 2020-11-04 12:21:40 | S0ix Exit 278 | 2020-11-04 12:21:40 | EC Event | AC Disconnected 279 | 2020-11-04 12:21:57 | S0ix Enter 280 | 2020-11-04 12:22:03 | S0ix Exit 281 | 2020-11-04 12:22:03 | EC Event | AC Connected 282 | 2020-11-04 12:22:35 | S0ix Enter 283 | 2020-11-04 12:22:47 | S0ix Exit 284 | 2020-11-04 12:22:47 | EC Event | AC Disconnected 285 | 2020-11-04 12:23:08 | S0ix Enter 286 | 2020-11-04 12:23:16 | S0ix Exit 287 | 2020-11-04 12:23:16 | EC Event | AC Connected Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09mb/google/dedede/variants: Update Power Limit2 minimum valueSumeet R Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value for dedede variants (baseboard and drawcia). Currently, variants like boten, waddledee, waddledoo, metaknight and wheelie uses the DTT entries from baseboard devicetree since there is no override present for these variants. So, these variants will also reflect this change of PL1 minimum value. For madoo variant, PL2 minimum value already set the same as PL2 maximum value. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on drawcia system Change-Id: I7ecf1ffcc7871192ebe18eb8c3c3fd3e1193721e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47154 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09mb/intel/jasperlake_rvp: Update Power Limit2 minimum valueSumeet R Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value for jasperlake rvp board. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on jasperlake rvp board Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-09soc/intel/*/chip: Remove unused devicetree entryPatrick Rudolph
InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-09mb/google/volteer/var/voema: config CSE LITEDavid Wu
Config voema to use CSE LITE BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voemaDavid Wu
BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-09mb/google/volteer: Skip TPM detection except on SPIJes Klinke
Production Volteer devices have Cr50 TPM connected via SPI, depending on Cr50 firmware version it may or may not support long enough interrupt pulses for the SoC to safely be able to enable lowest power mode. Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced with Dauntless, communicating via I2C. The I2C drivers do not support being accessed early in ramstage, before chip init and memory mapping, (tlcl_lib_init() will halt with an error finding the I2C controller base address.) Since the Dauntless device under development can be made to support longer interrupts, or a completely new interrupt signalling mode, there is no need to try to go through the same discovery as is done via SPI. This CL will skip the discovery, enabling the S0i3.4 sleep mode in all cases, on the reworked test devices. BUG=b:169526865, b:172509545 TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47049 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09mb/google/volteer/variants/volteer2: Tune I2C3 camera bus freq 400 kHzJohnny Li
The current I2C3 bus frequency is 341 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C3 frequency is 394kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: Ie1ef95bb39d71fbb113120a0ec88305bc23e7ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-11-09mb/google/puff/var/dooly: Set default I2C0 frequencyTony Huang
This setting copy from puff reference board and should measure again after whole system build. BUG=b:155261464 BRANCH=puff TEST=emerge-puff coreboot and check system speaker has sound output. Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47161 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-08mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard'Subrata Banik
List of changes: 1. Use devicetree.cb from default location 2. Create variant directory for ADL RVP with external EC as 'adlrvp_p_ext_ec' 3. Add initial overridetree.cb for 'adlrvp_p' and 'adlrvp_p_ext_ec' to override 'devicetree.cb' as applicable. 4. Move all common files between 'adlrvp_p' and 'adlrvp_p_ext_ec' to mainboard directory TEST=Build and boot both ADLRVP with onboard and external EC. Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47335 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07mainboard/ocp/tiogapass: Add xeon_sp pch.aslMarc Jones
Use the xeon_sp pch.asl to include the intel common lpc.asl. Change-Id: I22ee9d325888808a9c775ecee0591b661e2bba4e Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-07mainboard/ocp/deltalake: Use xeon_sp pch.aslMarc Jones
Use the xeon_sp pch.asl to pickup the common block lpc.asl. This allows deltalake to pick up any general pch asl updates. Currently, generates the same asl. Change-Id: I5005032b030d288fdf5ca2f99d21fe8e6c752037 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47304 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07mainboard/ocp/tiogapass: Set longer BMC timeoutMarc Jones
The BMC isn't always ready in 60 seconds if it printing debug output. Give it 90 seconds to finish before timing out in coreboot. Change-Id: I3932d3e8fad067e8971e82b45b499801fc78079f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Javier Galindo <javiergalindo@sysproconsulting.com>
2020-11-07mb/intel/adlrvp: Configure GPIOs to enable DMICSridhar Siricilla
The patch configures GPIO pins to enable DMIC. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-11-07mb/intel: Enable ALC711 Audio codec over SNDW0 linkSridhar Siricilla
The patch enables ALC711 Audio codec. Test=Verified on ADL RVP. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-11-07mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllersV Sowmya
This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers for ADLRVP. BUG=b:170607415 TEST=Built and booted on ADLRVP. Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47288 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07mb/intel/adlrvp: Configure the HPD GPIO'sV Sowmya
This patch configures the HPD1 and HPD2 GPIO's. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the hotplug functionality is working. Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-11-07vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark optionJonathan Zhang
Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD variables. FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP FSP binary, this option takes the space of UnusedUpdSpace0[0]. For DeltaLake mainboard, if corresponding VPD variable is set, use it to control the behavior. Such control is effective when FB's CPX-SP FSP binary is used. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-06zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT BoardLucas Chen
Adjust USB2 phy si setting fine tune on DVT for Ezkinil. BRANCH=zork BUG=b:156315391 TEST=Measuring scope timing and test usb detection Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-11-06mb/purism/librem_mini: Set unused GPIO pads to PAD_NCMatt DeVillier
Set numerous pads to PAD_NC as per board schematics (they are either NC, or connected to test pads), and adjust comments as needed. Change-Id: I4c2ab936256d0031d7a127fbeac42c8951a0b39f Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-06mb/google/volteer/var/elemi: Update gpio and devicetreeWisley Chen
Update gpio and devicetree for elemi. BUG=b:170604353 TEST=emerge-volteer coreboot and boot into kernel Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-06mb/google/variant/elemi: config CSE LITEWisley Chen
Config elemi to use CSE LITE BUG=b:170604353 TEST=emerge-volteer coreboot Change-Id: I31c7a743645d6a34ee34e750ba92c108b306ee09 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47019 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemiWisley Chen
BUG=b:170604353 TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I1a1ab6f3d57d5023523b85bfb00d48d8b70a6c1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-06soc/amd/picasso: Update coreboot UPD variable names to include unitsZheng Bao
Use command below to change the variable globally. sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \ --exclude-dir=build --exclude-dir=crossgcc` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-06mb/google/octopus/variants/garg: Add new LTE SKUKevin Chiu
Add new SKU definition: Garg360 (LTE DB,1A2C,TS, no stylus, rear camera) SKU ID - 39 BUG=b:170708728 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47015 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05soc/amd/picasso: move MAX_CPUS setting from mainboard to SoC KconfigFelix Held
Since the mainboard Kconfig is sourced before the SoC one, it would still be possible to override this setting at mainboard level, even though that shouldn't be needed. The maximum CPU count for Picasso is 8, since the chips have only up to 4 cores with up to two threads each. Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05mb/msi/ms7707/Kconfig: Drop invalid defaultsAngel Pons
The PCI ID corresponds to the iGPU, which is disabled in the devicetree. Also, the VBIOS file does not exist at the specified location. Change-Id: I4f128d3057dc7218f32320c4e23466eb31af4e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45672 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05mb/purism/librem_mini: Drop DW0/DW1 from GPIO config commentsMatt DeVillier
These are generated by inteltool + intelp2m and reflect the pad configuration of the vendor (AMI) firmware at a specific point in time, but do not always reflect the correct configuration of a given pad as per the schematics, so drop them. Change-Id: Ie337cca5bc0e87a5426cceae8d7ec29ab14a1729 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47200 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-05mb/intel/adlrvp: Add support for DDR5 memorySubrata Banik
This patch adds DDR5 memory configuration parameters to FSP. TEST=Able to build and boot ADLRVP with DDR5 memory. Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/purism/librem_cnl: Set SaGv to FixedHighAngel Pons
Since the Librem Mini does not run on battery power, SaGv has little benefits and noticeably slows down testing, since memory training is run twice. Disabling SaGv cuts the 30-second cold boot time in half. Change-Id: Ib02e42dcb4f20fdbdca85456c0dceafc59c782d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-11-04sb/intel/lynxpoint: Align LP GPIO ACPI with BroadwellAngel Pons
Move the `GWAK` method into the GPIO device, and have lpc.c include the LP GPIO code. All usages of `GWAK` on mainboards need to be updated. Change-Id: Id6a41f553d133f960de8b232205ed43b832a83d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46775 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/purism/librem_mini: Drop community comments in GPIO configMatt DeVillier
These add nothing useful to the GPIO config Change-Id: Ieecc9bd67d020e141c3a1f1d387034df5e563068 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47190 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/purism/librem_mini: Update GPIO configMatt DeVillier
Update GPIO config using a fresh dump of inteltool from the vendor (AMI) firmware on a Librem Mini v2, run through intelp2m with parameters '-p cnl -n -ii' Change-Id: I747415fb9ab7b21943d256d248729cb9e2b4b945 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47206 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPsMatt DeVillier
Change-Id: Id306100fc691dcbde48b65092d0be9d7e73c0722 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47189 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/purism/librem_mini: Reorganize devicetreeMatt DeVillier
Move registers under devices to which they belong. Change-Id: I61ca7c1db02646252d7421f8b79dfc8a40b2bdb5 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47188 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/purism/librem_mini: drop unused HeciEnabled registerMatt DeVillier
this should have been corrected as part of: commit 3de90d1 [soc/intel/cnl: Set Heci1Disable depending on devicetree config] Change-Id: I6a103a1de01fc258ef359258a8a64f4c5a181139 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47187 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/purism/librem_mini: Increase TDP/PL2 settingMatt DeVillier
PL2 was set artificially low during development when the active cooling fan was not functional, and never corrected once the fan was fixed. Raise PL2 to a value which works with both Librem Mini variants. Change-Id: Ie377392020f73359aed80ddae727adb6f8d06344 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-04mb/purism/librem_mini: Drop devicetree settings which default to 0Matt DeVillier
All chip registers default to 0, no need to explicitly set them. Change-Id: I056121170d22393484b0ee79bd0815452161a900 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-04mb/purism/librem_mini: drop SendVrMbxCmd from devicetreeMatt DeVillier
Not needed for this board. Change-Id: I15a68b59bc512e571b9590007ea64561b3f3dae1 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-04mb/samsung/lumpy: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I7ad79a31142af8ae1b62497ade0b4ba7bac3a93c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46214 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/ocp/deltalake: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl files are same. Change-Id: I5bd8fe629fb969ec14dd400b6463ee1592d6903b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46207 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/ocp/tiogapass: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl files are identical. Change-Id: Iffd6954dcb3f9fb8bcd89854d84f6944cb520dd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46208 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/samsung/stumpy: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: I0eda144f1a4f07ca82b3a799afcd8fc908419e69 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46215 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/roda/rk886ex: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I2eea24db6cfd260e0f36243e90a5e01b360f23fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04mb/google/link: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'dsdt.dsl' files are identical. Change-Id: I7d4fc3acd82023b007d80638bcb71476330ef320 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04mb/google/beltino: Convert to ASL 2.0 syntaxElyes HAOUAS
Built google/beltino (Monroe) provides identical 'dsdt.dsl'. Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04mb/intel/baskingridge: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'dsdt.dsl' files are identical. Change-Id: I5897397bdadf86214ceaf90d8cd706e10969d8c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04mb/google/volteer/var/voema: Update dq/dqs mappingsDavid Wu
Update dq/dqs mappings based on voema schematics. BUG=b:169356808 BRANCH=volteer TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1aae4286278e712bf29ebb15738477828d3f74d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-04soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATIONZheng Bao
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/intel/emeraldlake2: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: Idd2bf447975b4c9b2cd3b440505c0bd960374165 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04mb/getac/p470/acpi: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: Ifed93f4b0c360ec74f28926fb7cc9774ae03b8a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04mb/getac/p470/acpi/ec.asl: Remove duplicated codeElyes HAOUAS
"If(And(RFDV, 0x02)) {Or(Local0, 0x02, Local0)}" is duplicated. Change-Id: I91698fb308cd37c65aa65e563bcd88743097f56c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45865 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/emulation/qemu-aarch64: Add a timestamp regionArthur Heymans
The romstage region is moved up a bit more to satisfy the MMU. Change-Id: I00c2b4972495fa669d4dc2a52f298a0e4d0cf5ff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04mb/google/volteer: clang-format mainboard.cJes Klinke
This CL is entirely generated by running the automatic formatter on this one file. BUG=None TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-04mb/prodrive/hermes: Set tcc offset to 1Patrick Rudolph
Prevent early throttling when the ambient temperature is high. Change-Id: Ie6881c9c0942aae3e43509170352271a74244d42 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-03mb/google/volteer: Log EC events in case of S0ix resumeFurquan Shaikh
This change adds the callback `elog_gsmi_cb_mainboard_log_wake_source()` to volteer to enable logging of EC events in case of S0ix resume. BUG=b:172272078 BRANCH=volteer TEST=Verified that EC events are logged correctly for S0ix resume: 11 | 2020-11-02 14:11:05 | S0ix Enter 12 | 2020-11-02 14:11:08 | S0ix Exit 13 | 2020-11-02 14:11:08 | Wake Source | Power Button | 0 14 | 2020-11-02 14:11:08 | EC Event | Power Button 15 | 2020-11-02 14:11:17 | S0ix Enter 16 | 2020-11-02 14:11:21 | S0ix Exit 17 | 2020-11-02 14:11:21 | Wake Source | GPE # | 112 18 | 2020-11-02 14:11:21 | EC Event | Lid Open Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7aa9dc2470da3226925927f2a0cc39fdd426e3b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47142 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03soc/intel/broadwell: Relocate PCH ACPI filesAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46754 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03mb/purism/librem_cnl: Adjust in preparation for new variantsMatt DeVillier
- Move the SoC select to board config (vs baseboard config) - Qualify the VGA PCI ID and CBFS size values based on board selection - Move devicetree to variant dir and add Kconfig entry - Use a separate board_info.txt for the baseboard and each variant Change-Id: I4764f2c1243ea49bd08e0735865cc3cb7a66441f Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-03mb/purism/librem_whl: rename to librem_cnlMatt DeVillier
Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake, rename the baseboard so that boards using other 'cannonlake family' SoCs (e.g., Cometlake) can be added with minimal confusion. Rename the mainboard dir and baseboard name, and adjust any references to them. Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02mb/google/volteer/var/volteer2: Merge `common_soc_config`Angel Pons
SCONFIG complains because of the duplicate devicetree entry. Change-Id: Ibdd60efdbcee5bda7c570d4b98f29cc8ede584cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-02mb/google/volteer/variants: Describe USB ports in devicetreeDuncan Laurie
Add the USB ports to the devicetree for describing them in ACPI, including defining the port relationships and defining the reset GPIO for the bluetooth device. BUG=b:151731851 TEST=tested on volteer, all other boards were checked against the latest available schematic. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c Reviewed-on: https://review.coreboot.org/c/coreboot/+/46853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02mb/google/volteer: Add DB_USB3_NO_C option for DB_USB fieldDuncan Laurie
Define option value 6 for DB_USB where there is a Type-A port but no Type-C port on the daughterboard. BUG=b:151731851 TEST=build volteer boards Change-Id: I489d24316556dedfecd821e502f1461010b1400f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02mb/google/kukui: Enable MT8183_DRAM_EMCP for kakaduSunway
The Kakadu project will be using eMCP board design. BUG=b:171841122 TEST=Boots on chromebook Kakadu successfully. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46871 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb/google/octopus/var/fleex: Add variant.c into smm stageEric Lai
variant_smi_sleep is called in smm stage so we need to add variant.c into smm stage. Otherwise it will call the dummy one. BUG=b:168075958 BRANCH=octopus TEST=build image passed. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46847 Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb/google/volteer: New variant for Volteer reworked with DauntlessJes Klinke
For development of the firmware to run on the Dauntless TPM, a number of Volteer2 devices are being reworked to replace the H1 chip with probe wires to connect to an external Dauntless development board. Some modification to the AP firmware is required, not least because the Dauntless chip is connected via I2C bus, instead of SPI. Most of the Dauntless developers will not otherwise have a Chrome OS chroot. Because of the above, I think it makes sense to have a new variant, for the reworked devices, which I intend to create with this CL. BUG=b:169526865 TEST=abuild -t GOOGLE_VOLTEER2_TI50 -c max -x Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-02mb/google/dedede/var/metaknight: Generate SPD ID for supported partsTim Chen
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory part being added is: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR BUG=b:169813211 TEST=Build the metaknight board. Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-02mb/google/volteer/var/terrador: Enable SaGv supportDavid Wu
Enable SaGv for terrador. BUG=b:171763116 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-02mb/system76/lemp9: Enable battery charging thresholdsTim Crawford
Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45533 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb/google/volteer/variants/delbin: Update DPTF parameters for delbinFrank Chu
Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46676 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02volteer: Create voema variantDavid Wu
Create the voema variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171755775 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOEMA Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4e1872d1ebff6fefdfb232f1ff82fce95a1ec643 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47007 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb/google/octopus/variants/dood: Add G2Touch touchscreen supportKenneth Chan
Add G2Touch touchscreen support for dood. BUG=b:171526389 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen work. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ica7d893de285c2dd1efcd43ac74919bdd5d5ac17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46675 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02mb/google/zork/var/vilboz: Update touch screen power sequenceEric Lai
Add ELAN touch support and update Goodix settings. BUG=b:157265632 BRANCH=zork TEST=emerge coreboot and check both touch screen are workable. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/46929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-02mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh
This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-02mb/google/volteer: Disable DPTF active policy for terrador and todorDavid Wu
Terrador and Todor are fanless design, so disable DPTF active policy. BUG=b:171019363,b:170699797 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I53a33b8706d7a7d4013a2a5627a620223fcffc3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46874 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/volteer: Remove RIPTO support for cameraDaniel Kang
GPIO D4 was used for camera reset for both front and rear cameras (RCAM_RST_L/FCAM_RST_L) in RIPTO. For later volteer versions, GPIO F15 is dedicated to the rear camera reset (RCAM_RST_L). Before, BOARD_GOOGLE_VOLTEER flag was used for setting the right RCAM_RST_L per volteer version. However, we don't support RIPTO anymore. Also using flags for different volteer version support can be error-prone. Removing RIPTO support. BUG=b:171726823 BRANCH=none TEST=Build and boot volteer proto2 or later version. Camera should work without an issue. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I961fc17092887b4807c12c95f7139bb7e7b33e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46826 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30x86: Add a minimal example SoC along with a boardNico Huber
The min86 example SoC code along with the example mainboard should serve as a minimal example how a buildable x86 SoC code base can look like. This can serve, for instance, as a basis to add new SoCs to coreboot. Starting with a buildable commit should help with the review of the actual code, and also avoid any regressions when common coreboot code changes. As the example code itself is build-tested, it should advance with coreboot and can't rot like documentation might. It also serves as a check what APIs need to be implemented with the default Kconfig settings. Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30mb/google/volteer: Separate power resource for VCMDaniel Kang
The camera privacy LED blinks during the boot and this gives a wrong impression to the users that the camera is being used during the power up. The blink happens when the camera module is probed and a series of kernel patches and coreboot patches are being submitted to resolve the issue. The kernel patches are submitted to the chromium gerrit. https://chromium-review.googlesource.com/2403386 https://chromium-review.googlesource.com/2403387 https://chromium-review.googlesource.com/2403385 https://chromium-review.googlesource.com/2403384 https://chromium-review.googlesource.com/2403383 https://chromium-review.googlesource.com/2403382 https://chromium-review.googlesource.com/2403381 https://chromium-review.googlesource.com/2403380 This is to separate the power resource for the VCM so that it can be controlled by the driver and suppress the LED turn on. BUG=b:169049942 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check if it blinks. It should not blink. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tomasz Figa <tfiga@google.com>
2020-10-30mb/google/octopus/var/fleex: Disable XHCI LFPS power management by skuEric Lai
LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:169645448 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2020-10-30fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak
We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 10:06:55 +0000