diff options
| author | Frank Chu <frank_chu@pegatron.corp-partner.google.com> | 2020-10-23 16:42:41 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-02 06:22:05 +0000 |
| commit | 5b10ec43611156cc41ff5e081a547bc5344395a4 (patch) | |
| tree | 44abff33ab2fd51cb7fd2b405d9b100e08e4f498 /src/mainboard | |
| parent | 397b46c172d6d1c957d23bd3a1e660a468f7eecc (diff) | |
mb/google/volteer/variants/delbin: Update DPTF parameters for delbin
Configure board specific DPTF parameters for delbin
BUG=b:168958222
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46676
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/volteer/variants/delbin/overridetree.cb | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index ba02d8c55a..29012e6163 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -13,7 +13,78 @@ chip soc/intel/tigerlake register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + register "tcc_offset" = "8" + + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_TEMP_SENSOR_3, + .thresholds = {TEMP_PCT(57, 90), + TEMP_PCT(47, 80), + TEMP_PCT(40, 70), + TEMP_PCT(36, 60), + TEMP_PCT(34, 50), + TEMP_PCT(30, 40),}}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 6000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 75, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 80, SHUTDOWN)}" + + ## Power Limits Control + # 3-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is 15-51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 5200, 220, 2200, }, + [1] = { 80, 4900, 180, 1800, }, + [2] = { 70, 4600, 145, 1450, }, + [3] = { 60, 4200, 115, 1150, }, + [4] = { 50, 3800, 90, 900, }, + [5] = { 40, 3400, 55, 550, }, + [6] = { 30, 2900, 30, 300, }, + [7] = { 20, 2300, 15, 150, }, + [8] = { 10, 1600, 10, 100, }, + [9] = { 0, 0, 0, 50, }}" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 device ref i2c0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" |