diff options
| author | Benjamin Doron <benjamin.doron00@gmail.com> | 2020-11-05 22:20:52 +0000 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-09 21:34:42 +0000 |
| commit | ac6565279ce30e2eed8e5fcc14f687013717c82f (patch) | |
| tree | af980479dc647103e2e3d8493ff68c65be82d08a /src/mainboard | |
| parent | 136380fcac333ec28574f5bfb5b43b61a919130b (diff) | |
soc/intel/skylake: Enable PCH thermal depending on devicetree
Hook up PCH thermal subsystem configuration to devicetree.
Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/ramstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c index 962702fb5a..9518b1d721 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -13,7 +13,6 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->TurboMode = 1; - params->PchThermalDeviceEnable = 0; params->PchPort61hEnable = 1; params->CdClock = 3; } |