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2022-01-01src: Use 'stdint.h' when appropriateElyes HAOUAS
Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01src: Remove duplicated includesElyes HAOUAS
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-01mb/google/jecht/acpi: Replace LNot() with ASL 2.0 syntaxFelix Singer
Replace `LNot (a)` with `!a`. Change-Id: I4a9165b4610d7d035509b7f10eed0d9847afca1f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01mb/google/dedede/var/magolor: Set core display clock to 172.8 MHzRen Kuo
When using the default initial core display clock frequency, Magolor has a rare stability issue where the startup of Chrome OS in secure mode may hang. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommendation avoids this problem. Depend on CL: https://review.coreboot.org/c/coreboot/+/60009 The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0 (172.8 MHz) for magolor. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01mb/aopen/dxplplusu/acpi: Replace Decrement() with ASL 2.0 syntaxFelix Singer
Replace `Decrement (a)` with `a--`. Change-Id: I4320d86ce91e7070dc10fcefff6cbc0956be9788 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60586 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-01mb/aopen/dxplplusu/acpi: Replace Increment() with ASL 2.0 syntaxFelix Singer
Replace `Increment(a)` with `a++`. Change-Id: I52315e71a51de5c85f11d68854dfe68a474d5cbe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01mb/aopen/dxplplusu/acpi: Replace LOr() with ASL 2.0 syntaxFelix Singer
Replace `LOr (a, b)` with `a || b`. Change-Id: Ib563f8ce5873e53c94992d81e78118a1194fc9af Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01mb/google/jecht: Replace LOr() with ASL 2.0 syntaxFelix Singer
Replace `LOr (a, b)` with `a || b`. Change-Id: Ib34e8af6668e3c875fabd1fa84862109afa94d18 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01mb/aopen/dxplplusu/acpi: Replace LAnd() with ASL 2.0 syntaxFelix Singer
Replace `LAnd (a, b)` with `a && b`. Change-Id: Ifbd7b282061b27cda9d5d4c17e2ade9459e72c24 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60574 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-01mb/roda/rk9/acpi: Replace Multiply(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b)` with `a * b`. Change-Id: I8697f62cf5627ace8c4eac0caec7962171bb3541 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60567 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-01mb/google/kahlee/acpi: Replace Index() with ASL 2.0 syntaxFelix Singer
Replace `Index (FOO, 0)` with `FOO[0]`. Change-Id: I81a2d63db3e3575acd91ea99e1490701889b896f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-01mb/google/corsola: Initialize krabby displayRex-BC Chen
PS8640 is used on Krabby board as the eDP bridge IC. Enable PS8640 and configure display in mainboard_init() to support display in firmware screen. BUG=b:210806060 TEST=saw firmware display on eDP panel of krabby and kingler. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I314d5407c40429bb7bc50f36fece58e396b27548 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60447 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-01mb/google/corsola: Remove 'corsola' from Kconfig board namesRex-BC Chen
The 'Corsola' (MT8186 Chromebooks) family has two reference designs (Krabby and Kingler) and all real implementations should follow either one of the two. To prevent confusion, we should remove the 'corsola' configuration from Kconfig board names. BUG=b:210806060 TEST=emerge-corsola coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib354054e358c0783f6221c2e2a1730b5c6ddba33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60515 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-01soc/mediatek/mt8186: Add support for regulator VRF12/VCN33Rex-BC Chen
To provide power to PS8640, the eDP bridge IC on krabby, add control of VRF12 and VCN33 to set voltage from MT6366. TEST=measure 1.2V from VRF12 and 3.3V from VCN33. BUG=b:210806060 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-31mb/google/brya/{brask,gimble}: Use eNEM for CAR by defaultSubrata Banik
More Brya variants like Brask and Gimble have migrated to use Alder Lake QS SoC which enables eNEM feature by default. Hence, select eNEM for CAR by default for these variants. BUG=b:168820083 TEST=Able to build and boot gimble variant using eNEM mode. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie5734606e58410545a5f5421837080680664707f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-31mb/google/slippy/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: I1f18a327b5500eacfe8895ebabb1f2b294cef0d0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31mb/google/kahlee/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: If80d97abc831e17bc8bc6e379bbae26e65db23f1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31mb/google/cyan/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: I771c855e8885238c7fc3b0a7a6e9c2002274c0f2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31mb/google/jecht/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: Ie7fa132623c7834e3d2f1acda032928579819a84 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31mb/roda/rk9/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: If2bb935570b1cb2b7a5e4168d594d735f343369b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31mb/aopen/dxplplusu/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: I22088a584c1d6d5188cb74ff8b03f51ea02e4b68 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30mb/google/jecht/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b, c)` with `c = a - b`. Change-Id: I604a5c56e1941dd2932eaa5b44966e6ea06abb4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30mb/google/cyan/acpi: Use ASL 2.0 syntax to access arraysFelix Singer
Replace Index(FOO, 1337) with FOO[1337]. Change-Id: Ica59483c9e9f67361d269259708998f9152406f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30mb/51nb/x210/acpi: Use ASL 2.0 syntax to access arraysFelix Singer
Replace Index(FOO, 1337) with FOO[1337]. Change-Id: I5692d1be5a94d259bbed987a43ec17ad1c1f915c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30mb/google/beltino/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I3f4ac9ba134e20cc1808de125f87b84f86567303 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/google/octopus: Drop unnecessary optionFelix Singer
Since all variants select the option `BASEBOARD_OCTOPUS_LAPTOP`, drop it and move its selects to the common baseboard. Change-Id: Ia3d220401eeaa4255d6a4472eeed15c51f6a81a9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-29mb/google/octopus: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I5949fc474c4923beb1f41a40876f03e5c70fc5b1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-29mb/purism/librem_cnl/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I587dcd8fc208562ecf0e0ba6ea9f741538511192 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/google/jecht/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ie54637c451252fd38aab9207ab0b846cc50f4b12 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/google/kahlee/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ib5ccba321f3cb737eb6287472314b06ebe6e2437 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/google/slippy/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I8c0d1aaccb729eab91c88c77c5efc53d3e951692 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/google/zork/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I433b7138da84b57e45e816ab116f8ca874fdc0e0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/google/auron/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ib06452c7b89c328d124e98669178b5dd3fc235f8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/hp/pavilion_m6_1035dx/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Idf84b7333e94dfa9caf0aa477b87e3156c24d5cd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/lenovo/g505s/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ibc775cda61134523dc03a073676b9d035ea48472 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/roda/rk886ex/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I6091d81d49e5ae6bf30a03d2fb2d54f0ec6533d1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/roda/rk9/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ic461c109b3c6d08cc3cda60f23e673157cd782f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/google/corsola: Initialize kingler displayRex-BC Chen
ANX7625 is used on Kingler board as the eDP bridge IC. Enable ANX7625 and configure display in mainboard_init() to support display in firmware screen. BUG=b:209930699 TEST=saw firmware display on eDP panel of kingler board. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie8de5d8ba150d3ae086c7635601dbc0846aebe91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-29mb/google/corsola: Add board common config for kingler and krabbyRex-BC Chen
Add common configs to help implementing board-specific logic (for example using different eDP bridge IC drivers). BUG=b:209930699 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If775532c1a262f3e8b3f11b24cae555844f2bfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-29mb/google/corsola: Fully calibrate DRAMRyan Chuang
Initialize and calibrate DRAM in romstage. DRAM full calibration logs: dram_init: dram init end (result: 1) DRAM-K: Full calibration passed in 20014 msecs TEST=DRAM full calibration pass. BUG=b:202871018 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I80a18a8be5b1d47a5f0f7afed9601c0884e69035 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-28mb/google/brya: Reorder selects alphabeticallyFelix Singer
Change-Id: Ie03f7049b013648372b002ce9b731589b1fffabd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60371 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-28mb/google/volteer/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I2416456bd447a6296ca3fac6cf90aa2e78f6de57 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/deltaur/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I36a02f8d509ef39983b4162188abc0cbc3d570cf Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/cyan/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I445dbe5d1f744c6512d618efdc927509d5ba291f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/auron/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I1c438e53adc835df0a3f9436f94e0f5341cf79dd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/beltino/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: If4ba4b2a7a358ad86b547b16a12593b912f9bd8f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/jecht/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I2287ae1357e0f02a42ebd770ee799613fd29c033 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/slippy/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I7691cf37da03e6a689efcb84527ba519fe661258 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/butterfly/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: Ifc6708c2e864e5dcba12d53af24993dc173fca7f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/link/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I019ba38015b245f69c9663fd93775409c7d9cb1b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/parrot/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I7e99a44dcb512f0eb4355663cdc8dac690211dab Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/stout/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: Icd58cd466c8e85625170bb14e66fc068758883f5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/rambi/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I22e189dfa9b8944341aafcafe4e97dca65558937 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-28mb/google/octopus/Kconfig: Reorder selects alphabeticallyFelix Singer
Change-Id: I545a1111e24f45f732f1c325c808737dfb6bcae6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-26mb/google/brya: Rework BOARD_GOOGLE_BASEBOARD_* KconfigSubrata Banik
Current mainboard code supports different baseboard binding example: brya uses BOARD_GOOGLE_BASEBOARD_BRYA and brask uses BOARD_GOOGLE_BASEBOARD_BRASK Kconfig. This patch makes the `BOARD_GOOGLE_BRYA_COMMON` Kconfig default `n` and specific baseboard binding Kconfig can select this Kconfig. It would also avoid adding if clause for specific baseboard binding Kconfig everytime with introduction of newer mainboard in future. TEST=Verified CONFIG_BOARD_GOOGLE_BRYA_COMMON=y while building brya and brya coreboot.rom remains the same. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I754159447e68b8ac2ea21009cc801fc5ba5df56e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-26mb/google/brya: Move PCH selection to variant configSubrata Banik
This patch ensures ADL-P PCH can get selected by mainboard variants to accommodate mainboards with ADL-N PCH in future. TEST=Able to build and boot brya without any Kconfig change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifbcd1cd7f8ecafee22d50c3f3f20decc4cc62797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60378 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-26mb/google/brya/var/taeko4es: Set vGPIO reset typeJoey Peng
Copied from commit df72b18d (mb/google/brya/var/taeko: Set vGPIO reset type).Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack. BUG=b:207070967 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-26mb/google/guybrush/var/dewatt: update telemetry valueKenneth Chan
AMD SDLE testing had been done and apply the following telemetry settings for dewatt: vdd scale: 95359 vdd offset: 449 soc scale: 31481 soc offset: 193 BUG=b:211566312 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I597a51ca599eff2abc9640aba5f3c804a686f057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-24mb/google/brya: Allow variants to choose CAR setup configurationSubrata Banik
Lists of changes: 1. Create choice config to let ADL mb variants to pick the desire CAR setup configuration between NEM and eNEM, where NEM and eNEM Kconfig have selected its required IA SoC common CAR Kconfig to able to perform the early boot configuration using CAR. 2. Lists of variants (kano, redrix, and felwinter) to drop INTEL_CAR_NEM Kconfig select and choose eNEM. 3. Default CAR configuration for ADL mb is still NEM due to still using older SoC skus without eNEM support enabled. BUG=b:168820083 TEST=Able to build and boot P2 boards using eNEM mode. Change-Id: Ibe94e6b82739ec65829859271622d904d75e978d Signed-off-by: subratabanik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-24mb/google/drallion: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I4de9bc426b92d57d6aabe17cceddf6b6aa444327 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/drallion/Kconfig: Restore alphabetical order on selectsFelix Singer
Change-Id: I31df9c339821074493329f6ed8fb1559b9e1a793 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/hatch: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: Idb7fcaaa175eb5b6e953ad0d5e2c5757d18838e4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/hatch: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: I6698c3882a3019e7e8f86fcb4e1c456e362d74b1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/hatch/Kconfig: Put baseboard option before variantsFelix Singer
Align with other mainboards and put the baseboard option before the variants ones. Change-Id: I314239b6d5abd531ccdcbe4426b2c7956dc9ae45 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/sarien/Kconfig: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I52c79f8958c5c40a258bcc292702154765afc476 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/sarien: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: Ia9c59917196df8226391765f7dd7b7c5cdad1aee Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/sarien: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: I013a6250727040c289244c31fbfbffef5ed0730b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/reef: Drop unnecessary optionFelix Singer
Since all variants select the option `BASEBOARD_REEF_LAPTOP`, drop it and let the common baseboard option select it. Change-Id: I7f2ffd1e7b9ad2fab500b83c4cc56c9fc2d161ab Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-24mb/google/taniks,vell;mb/intel/adlrvp_n_ext_ec: fix build errorFelix Held
Commit d448f8ce0fe9955e7792f54cc278897152d53590 (drivers/intel/pmc_mux/ conn: Change usb{23}_port_number fields to device pointers) changed the way the pmc_mux/conn driver gets the corresponding USB ports from the devicetree. This change didn't include the corresponding change for the Taniks and Vell variants of the Google Brya project and the Intel adlrvp_n_ext_ec board which probably weren't in the tree at the time the patch referenced above was created. This patch ports the needed change forward to those boards to fix the build of the upstream tree. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-24mb/intel/adlrvp: Configure GPIOs for Alder Lake-NUsha P
List of changes: 1. Add separate file for ADL-N GPIOs 2. Configure GPIOs as per the schematics of ADL-N RVP Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2021-12-23mb/google/hatch/var/scout: improve USB2 port 4 strengthKenneth Chan
Set USB2 port 4 pre emphasis to 15mV for passing USB2 port 4 SI (margin eye diagram). BUG=b:210755120 TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for measuring USB2 port 4 eye diagram. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb: Remove dot from end of non-sentence commentPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,' Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb: Add space before closing comment block keywordPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'ramstage\*/' | xargs sed -i 's,ramstage\*/,ramstage */,' Change-Id: Ied155d325846fc0ef3e823e5708c6f74e3d7998f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23ChromeOS: Refactor ACPI CNVS generationKyösti Mälkki
Remove chromeos_dsdt_generator() calls under mainboard, it is possible to make the single call to fill \CNVS and \OIPG without leveraging device operations. Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/taniks: Include driver for GL9763E for eMMC boot diskJoey Peng
Support GL9763E as a eMMC boot disk BUG=b:210089379 TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taniks. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Iab0fd88ac88e07a8580426234adc9c21df6c11d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/brask: Customize LEDs of RT8125Rory Liu
Add Kconfig item RT8168_SET_LED_MODE to enable LED customization. Update the LED settings in devicetree. BUG=b:193750191 TEST=Try different register values to verify LED feature. Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com> Change-Id: If80ace497c7481ce40b55af7e17e12a286aa9164 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/vell: Add Hynix LP5 DRAM supportKevin Chiu
Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell: DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 1 (0001) BUG=b:204284866 TEST=emerge-brya coreboot Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/variants/primus: remove board_id check for ALC5682I-VSMalik_Hsu
The board ID check for audio codec is no longer required, therefore remove it. BUG=b:210705216 TEST=emerge-brya coreboot chromeos-bootimage and check audio function Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ifbe838186da2e64737a9ffb557cf324124e79a9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/gimble4es: Configure Acoustic noise mitigationMark Hsieh
- Enable Acoustic noise mitigation - Copied from gimble set slow slew rate VCCIA and VCCGT to 8 BUG=b:206704930 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/dedede/var/magolor: Add stylus functionRen Kuo
Add the stylus field in fw_config. Update devicetree and gpio to handle stylus pen detection. BUG=b:167983049 TEST=Build firmware and check behavior as following: 1) Set the fw_config "bit4=1" for pen present: Wake up from suspend when pen is removed from the garage. Present the stylus menu when pen is removed from the garage. 2) Set the fw_config "bit4=0" for pen absent: Wake up and present menu will not work when pen is removed form the garage. Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23mb/asrock: Add ASRock H77 Pro4-M mainboardMichael Büchler
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM. The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot. Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.15.0 to boot slackware64 - SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10 Not working: - Booting from the two SATA ports provided by the ASM1061 - Automatic fan control with the NCT6776D Super I/O Untested: - VBT (it is included, though) - Infrared header Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb/google/guybrush/var/dewatt: update DRAM ID tableKenneth Chan
1. Samsung LPDDR4X 4266 4G K4UBE3D4AB-MGCL 2. Hynix LPDDR4X 4266 4G H54G56CYRBX247 (already used by other variants) BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed Reviewed-on: https://review.coreboot.org/c/coreboot/+/60090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Update the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. vdd scale: 73457 -> 73331 vdd offset: 291 -> 1893 soc scale: 30761 -> 31955 soc offset: 834 -> 852 BUG=b:207299255 BRANCH=guybrush TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE/Stardust test Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/intel/adlrvp_n: Add support for ADL-N LP5 RVPKrishna Prasad Bhat
Add support for Alder lake N LP5 RVP with board ID 0x7. Since SPD index 7 is unused earlier, ADL-N will use it. Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-12-23mb/google/dedede/var/beadrix: Remove SD controllerTeddy Shih
Remove SD controller configurations based on the beadrix's schematic. BUG=b:204882915 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Iba6f5cbbe90d9307e5e8080d7063a1881acd7ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60266 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23mb/google/dedede/var/beadrix: Add internal USB camera supportTeddy Shih
This change adds internal USB camera into devicetree for beadrix. BUG=b:204882915, b:210772511 BRANCH=None TEST=Built and checked camera device existence with lsusb Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/dedede/var/beadrix: Enable audio featureTeddy Shih
This change adds ALC5682I audio codec and MAX98360A amplifier for beadrix. BUG=b:204882915, b:210756131 BRANCH=None TEST=Built and heared speaker sound on OS Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I6f12f71ec66acd420471ab9a7612b1821650ad54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/dedede/var/beadrix: Enable PIXA touchpadTeddy Shih
This change adds PIXA touchpad into devicetree for beadrix. BUG=b:204882915, b:203113111 TEST=Built and verified touchpad function Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/starlabs/labtop: Update VBTSean Rhodes
Using Vbt.bin version 244, with the following changes: * Add 200ms delay to sink (T3) to avoid no response to AUX Channel transaction, which manifests as a repeating, colourful flicker. * Increase maximum supported refresh rate to 120Hz Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/59727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-23mb/google/dedede/var/cret: Generate new SPD ID for new memory partsDtrain Hsu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 BUG=b:203837656 BRANCH=dedede TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/brya/var/anahera: Enable SaGvWisley Chen
Enable SaGv support for anahera/anahera4es. BUG=b:211362081 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/taeko4es: Fix PLD group order (W/A)Joey Peng
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman
Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-23mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for ↵Kenneth Chan
USB ports Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4). BUG=b:199468920 TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/google/brya/var/vell: update overridetree for SSD setting=
Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics BUG=b:208756696 TEST=emerge-brya coreboot Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/vell: update overridetree for touchpad=
update override devicetree for touchpad based on schematics BUG=b:209554950 TEST=emerge-brya coreboot Change-Id: I835958349537ed490191db7c8e35847630de64ed Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/intel/{adlrvp,sm}: Remove unused header `helpers.h`Subrata Banik
This patch removes unused header inclusion as <commonlib/helpers.h> from several mainboard gpio definition files. Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae Signed-off-by: subratabanik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-22mb/google/brya/var/taeko: Enable Bayhub LV2 driverTim Wawrzynczak
Some SKUs of google/taeko have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:204343849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/60017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-22mb/google/brya/var/gimble: Configure GPIO to release PERST# earlierMark Hsieh
This change in power sequencing appears to fix issues with power consumption of the SD card controller. Possibly this change ensures the device has enough time to properly initialize itself after reset is deasserted but before it is accessed. BUG=b:206014046 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>