diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2021-12-20 13:55:57 +0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-23 14:34:16 +0000 |
| commit | ae8004ad5fdff6e1b7576a6718137105b17d9319 (patch) | |
| tree | 1169c1c0d8d5374f6aa588707f72d3b83e3b9be4 /src/mainboard | |
| parent | 591789b50bc8a2ef3f679d7790397b6eaabfae09 (diff) | |
mb/google/brya/var/anahera: Enable SaGv
Enable SaGv support for anahera/anahera4es.
BUG=b:211362081
TEST=FW_NAME=anahera emerge-brya coreboot
Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera/overridetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera4es/overridetree.cb | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 97be625f1c..1038798035 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -33,6 +33,7 @@ chip soc/intel/alderlake register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" + register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index 97be625f1c..1038798035 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -33,6 +33,7 @@ chip soc/intel/alderlake register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_5]" = "0" + register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |