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2024-01-18mb/google/nissa/var/craaskov: Add fan performance controlRex Chou
Add 6w and 15w fan performance control. BUG=b:318454915 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: If21baa2f6f9bcd527cec2bced27c5fb2cd607830 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79988 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18mb/google/nissa/var/craaskov: Modify 6W and 15W DPTF parametersRex Chou
1. Modify 6w/15w DPTF parameters based on b:290705146#comment41. 2. 6W MSR power limit_1 power (Watts) increase to 20. 3. 15W MSR power limit_1 power (Watts) increase to 20. BUG=b:290705146 TEST=emerge-nissa coreboot chromeos-bootimage Thermal team test pass. Change-Id: I15fa4b8f7c7088ff56da6493659ae45572913b5a Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-18mb/google/brox: Fix user facing camera acronymShelley Chen
I got confused and used UFS (User Facing Side) for the User Facing Camera (UFC) in the FW_CONFIGs. Change references of the camera from UFS --> UFC. BUG=b:300690448 BRANCH=None TEST=None. The camera has not been enabled yet. Change-Id: I4f8240ae51aad1e077f325a9eab5a2a92f1402cb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79997 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17soc/intel/elkhartlake: Drop redundant PcieRpEnableNico Huber
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-17mb/google/poppy: Use chipset dt reference namesMarvin Evers
Use the references from the chipset devicetree as this makes the comments superfluous. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-17mb/google/nissa/var/craaskov: Modify ELAN touchscreen enable delay from 1ms ↵Rex Chou
to 6ms Modify touchscreen enable_delay to 6ms to meet with spec. eKTH3915N_Product Spec_V1.3_20221028_IPM.pdf BUG=b:318443640 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id57ab04e61d9e95c962f2c564d3a7e2e7ed6b992 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79978 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2024-01-17Reland "Kconfig: Bring HEAP_SIZE to a common, large value"Patrick Georgi
This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-17mb/google/nissa/var/gothrax: Tune eMMC DLL valuesSimon Yang
Gothrax cannot boot into OS with a kernel loading failure. Update eMMC DLL values to improve initialization reliability How to get these values: - Sending different speed TX/RX command/data signal to eMMC and check the response is successful or not. - Collecting above results from each eMMC model that project used. - Analysing logs to provide a fine tuned DLL values. BUG=b:310701323 TEST=Cold reboot stress test over 2500 cycles Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-17mb/google/brox: Move storage devices to overridetreeShelley Chen
These are specific to the brox board, so moving devices to the brox variant. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-17mb/google/brox: Set up FW_CONFIGShelley Chen
Brox project has FW_CONFIG bits already set up in the project file for the retimer and for storage, so make sure that the brox device tree matches those settings. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79854 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-16mb/google/nissa/var/craaskov: Add Micron MT62F1G32D4DR-031 to mem_partsIan Feng
Add new memory Micron MT62F1G32D4DR-031 WT:B. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 2 (0010) BUG=b:319778218 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79914 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/lenovo/x230: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I38ef315dbdadb140e8e7163e755a078bc906e1b5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t430: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ib94dd2778cf89ae8b97b43031d729c728f59a29e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t530: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ied9f37355432d58f83cb8453111a261c4eddc14a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/x220: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/x220 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/x220: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: Ife8f3bc8b7fd14bb9a0e8dd4bc3d33b44c8f794f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asrock/b75m-itx: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I369ae1fd66326a2cbfa3fe155b0118251e2272d9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-by: Janik Haag Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/h61-series: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from asus/h61_series are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I1ba2cb08e60cf806c5d749be15265e577a7abc25 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/h61-series: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I8008fcc994e49c1626fd366c74661fcceb21a323 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/maximus_iv_gene-z: Remove superfluous comments from dtFelix Singer
Since all devicetrees from asus/maximus_iv_gene-z are using the reference names for PCI devices, remove the equivalent comments documenting their function. Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/asus/p8x7x-series: Use chipset dt reference namesFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: I50250fcf4105f39e55e8837613880bfe5c69deef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79967 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/lenovo/t520: Remove superfluous comments related to PCI devicesFelix Singer
Since all devicetrees from lenovo/t520 are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I307dbf7a7d6fc9086e868d8315ba7a66b94a24e7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-14mb/lenovo/t520: Convert remaining PCI numbers into reference namesFelix Singer
Change-Id: I18ce899516fd38b21ded1e3144aa22e705c534b8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79965 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/google/geralt: Enable IVO_T109NW41 MIPI panel for CiriRuihai Zhou
The IVO_T109NW41 will be the second source MIPI panel for Ciri. BUG=b:319025360 TEST=boot Ciri with IVO_T109NW41 panel, see firmware screen BRANCH=None Change-Id: I9dc2228d39bb8bb048d1f37727c96b0ad621e912 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-01-14mb/google/geralt: Enable BOE_NV110WUM_L60 panel for CiriRuihai Zhou
The MIPI panel BOE_NV110WUM_L60 will be used for Ciri, enable it. Also remove the `mdelay(10)` after mtk_i2c_bus_init, because MTK confirms this is not needed. Add mdelay(2) between VDD18 and VSP/VSN to meet the panel datasheet. BUG=b:308968270 TEST=Boot to firmware screen BRANCH=None Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78957 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-14mb/hp/compaq_elite_8300_usdt: Add VBTRiku Viitanen
Extracted from a system running OEM BIOS v03.08 (latest as of now). Build-tested and boots Linux (through SeaBIOS). Command used: intelvbttool --inlegacy --outvbt data.vbt Change-Id: Ibd999d30d6e8fea1368afae67f4dc1c3039d3ae1 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-13tree: Remove duplicated includesElyes Haouas
Change-Id: I09dd5871cb366ef95410efc1ca6c4337f23b52fd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79912 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-13lib/smbios: add segment_group parameter to smbios_write_type9Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I48b393913913db8436f5cbca04d7411e68a53cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-13mb/google/brox: Enable Elan trackpadShelley Chen
BUG=b:311450057,b:300690448 BRANCH=None TEST=to be tested on a device with i2cdetect Change-Id: If6da1c722e87a50c6d422b300f16a52d884fa08f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-13mb/google/brox: Configure vGPIOs for NVMeShelley Chen
This is needed for NVMe to work when PCIe device is connected to the CPU side of RPL soc. BUG=b:311450057,b:300690448, b:319058143 BRANCH=None TEST=Tested on device and was able to boot to the OS Change-Id: Ic8a1fdcedf2ec6c7bf1dd00e02ef7c13e9338aac Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-13mb/google/brox: Disable package c state demotionShelley Chen
This needs to be disabled for RPL otherwise we'll hit the assertion: [EMERG] ASSERTION ERROR: file 'src/soc/intel/alderlake/fsp_params.c', line 1066 There is a comment in the referenced file/line in the assertion that says that "C state demotion must be disabled for Raptorlake J0 and Q0 SKUs." So, disabling it. BUG=b:311450057,b:300690448 BRANCH=None TEST=Tested that we didn't hit this assertion on the device after this change Change-Id: Ib7b2484de2d84c980550fd951f1e30efab0ee197 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79855 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-12mb/google/nissa/var/anraggar: add FW config to apply the wifi sarJianeng Ceng
1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings. - WIFI_6 for MTK Wi-Fi module MT7921L - WIFI_6E for Intel Wi-Fi module AX211NGW BUG=b:315418153 TEST=emerge-nissa coreboot Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-01-12mb/google/nissa/var/quandiso: Tune P-sensors for Linux 5.15 sx9324Robert Chen
driver Since DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER value on dedede cannot meet DRIVERS_I2C_SX9324 on nissa, need to update the tuning value. Update proximity sensor fine tune value with quandiso EVT machine. BUG=b:314550601 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and verify p-sensor watch 'cat /sys/bus/iio/devices/iio:device*/*raw' Change-Id: I5fc3bc5876594f2df79d628bd986113d37087c3d Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-12mb/pcengines/apu2/Kconfig: select HUDSON_FADT_LEGACY_DEVICESFelix Held
The APU boards have an NCT5104D chip on the LPC bus that implements some serial ports that have the legacy IO port interface to the host and doesn't describe this in the ACPI tables, so select HUDSON_FADT_LEGACY_DEVICES to have the corresponding FADT bit set. Since this chip doesn't provide an 8042-compatible keyboard controller, don't select HUDSON_FADT_8042. TEST=Surprisingly, this doesn't seem to make a difference to the Linux kernel; is creates all ttyS[0..3] devices with and without this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8872b8c3d6e0610630ba17a0fccdcf8cebb1d3c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-12sb/amd/pi/hudson/Kconfig: replace HUDSON_LEGACY_FREE optionFelix Held
HUDSON_LEGACY_FREE controlled both if the legacy devices and the 8042 flags are set in the IA-PC boot architecture filed of the FADT. Since some systems have legacy devices on the LPC bus, but no 8042-compatible keyboard controller, replace this option with the two new options HUDSON_FADT_LEGACY_DEVICES and HUDSON_FADT_8042. TEST=The FACP table doesn't change on APU2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ff85630c90fb2ae8c8826bbc9049a08668210d Reviewed-on: https://review.coreboot.org/c/coreboot/+/79893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-11mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodesFelix Held
Tell binaryPI to not disable the LPC decodes for the IO ports used by the serial ports on the Super I/O chip during the AmdInitReset binaryPI entry point. Checked the Stoneyridge binaryPI source code which is closely enough related to be reasonable sure that this option only controls which LPC decode bits get cleared and won't have any other side effects. TEST=Now the full console output from the APU2 board gets printed on the serial console. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I91ef4423bd7bf6c1d7a175336f0f89479f2cde02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79852 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11mb/starlabs/starbook/rpl: Enable C1eSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3a317d031e71f86afc50b229d1b97197552f4fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-11mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSPLean Sheng Tan
Update the VBT version from 249 to 251. It is the same VBT settings as the previous one, but update it based on ADL-P MR5 FSP so it will work with MR5 GOP driver to fix the error "no graphic HOB found". Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79020 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-11mb/google/nissa/var/craaskov: Enable PIXA touchpadIan Feng
Add PIXA touchpad for variants of craaskov. BUG=b:289962540 TEST=build craaskov firmware and test with PIXA touchpad Change-Id: Iccf19b275548f44aec00be8631590b8a7ad1aa23 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79872 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-01-11mb/google/rex: Remove redundant HAVE_FSP_LOGO_SUPPORT configSubrata Banik
Removes unnecessary HAVE_FSP_LOGO_SUPPORT config from google/rex baseboard. Intel Meteor Lake SoC now selects this config automatically for supported platforms. BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex and intel/mtlrvp. Change-Id: I89bdd54cb73b11f74db2927a5eb86ab826c60517 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79860 Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10mb/google/nissa/var/anraggar: Add FW_CONFIG probe for mipi cameraWeimin Wu
Due to some without mipi camera SKUs can't entering S0i3. BUG=b:317670018 TEST=suspend_stress_test -c 1 Change-Id: Ifa8649a603c59946b530abd315113b405ceaf35a Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-10mb/google/byra/var/*: Set WLAN device type back to pciDavid Ruth
This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the WLAN device type to generic broke ACPI SSDT table definition, so set it back to pci. BUG=b:318576073 TEST=build/boot google/nissa (pujjo), verify WLAN ACPI SSDT tables contain the appropriate device entry. Change-Id: If5dad9deb040c8cb0c507e11726f0ba44ccb2909 Signed-off-by: David Ruth <druth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-01-10mb/google/cherry: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on dojo Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-10mb/google/corsola: Use common mtk_display_init()Yidi Lin
TEST=check FW screen on Steelix, Tentacruel and Starmie Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79777 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10soc/mediatek: Add common implementation to configure displayYidi Lin
The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on() - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to mediatek/common/display.c and refactors `struct panel_description` to generalize the display init sequences. configure_display() is also renamed to mtk_display_init(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79776 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-10mb/intel/mtlrvp: define a new config for Chrome ECDeepti Deshatty
Introduce new config MTL_CHROME_EC_SHARED_SPI, tailored for Chrome ECs utilizing an external shared SPI flash. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Cq-Depend: chrome-internal:6691498 Cq-Depend: chrome-internal:6741356 Change-Id: I462c34c5adaefa37c652de293152243c58bad7c5 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-10mb/intel/mtlrvp: streamline Chrome EC configsDeepti Deshatty
Chrome EC configuration options that are common among various boards have been consolidated under the "BOARD_EXT_EC_SPECIFIC_OPTIONS" config. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79211 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-09mb/ibm/sbp1: Set FSP loglevelPatrick Rudolph
Change-Id: Ia97dbda30f657f0b1568364d712eaea8d134b3b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79791 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-09mb/google/brox: Fix error in DDR DQS configShelley Chen
The DQS mapping for DIMM idx 6 was discovered to be incorrect to what was in the schematics. Correcting the mistake in this CL. BUG=b:311450057,b:300690448 BRANCH=None TEST=tested on device and it passed memory training Change-Id: I21f50e2f5b4fae09725c1c7532636ed1cc1a9043 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79843 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2024-01-08arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORTFelix Held
Introduce the HAVE_CONFIGURABLE_APMC_SMI_PORT Kconfig option that when not selected will result in a default implementation of pm_acpi_smi_cmd_port to be included in the build that returns APM_CNT. SoCs that provide their own pm_acpi_smi_cmd_port implementation, need to select this Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaceb61b0f2a630d7afe2e0780b6a2a9806ea62f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-01-08mb/google/nissa/var/craaskov: Implement touchscreen power sequencingrex_chou
For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:317746281 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79764 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05mb/hp/z220_series: Rename to snb_ivb_desktopsRiku Viitanen
In preparation for adding other similar boards under it as variants. Tested that z220_cmt still builds. Change-Id: I96dec173e0d97d8564bad14778333b8231684ef8 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79434 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.aslFelix Held
To avoid code duplication and to also bring the mainboards using the Picasso SoC more in line with Cezanne and newer, factor out the SoC- specific code from the mainboard's dsdt.asl files to the SoC's soc.asl. TEST=Timeless builds result in identical images for Bilby, Mandolin, and Zork/Morphius Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-03mb/intel/mtlrvp: add 512KB SI_EC FMAP regionDeepti Deshatty
This patch introduces the 512KB SI_EC FMAP region for storing the EC firmware, a necessary addition to support EC chips without internal flash memory. As a testing platform, the MTLRVP Chrome SKU is utilized in conjunction with the Microchip EC1723, and the changes are verified. Cq-Depend: chrome-internal:6691498 Cq-Depend: chrome-internal:6741356 BUG=b:289783489 TEST=build "emerge-rex coreboot chromeos-bootimage" is successful. changes are verified. EC Log: 23-11-06 17:46:49.564 --- UART initialized after reboot --- 23-11-06 17:46:49.564 [Image: RO, mtlrvpp_m1723_v3.5.142816-ec:6596a3, os:f660f7,cmsis:42cf18,picolibc:6669e4] 23-11-06 17:46:54.609 D: Power state: S5 --> S5S4 23-11-06 17:46:54.620 D: Power state: S5S4 --> S4 23-11-06 17:46:54.620 D: Power state: S4 --> S4S3 23-11-06 17:46:54.642 I: power state 10 = S3S0, in 0x0087 23-11-06 17:46:54.642 ec:~>: Power state: S3S0 --> S0 Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79209 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-03mb/google/rex/var/screebo: Prevent camera LED blinking during bootJason Chen
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot, preventing privacy LED blink. BUG=b:317434358 TEST=none Change-Id: I43044e64c2c3a645ec0cad2ac903cc19ac89c9af Signed-off-by: Jason Chen <jason.z.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79803 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2024-01-02mb/google/fizz: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I7752819091e2a75c8d818f7d0cf90eabc11c4759 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02mb/razer: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built razer/blade_stealth_kbl with BUILD_TIMELESS=1 and the resulting binary remains the same. Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02mb/intel/kblrvp: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Marvin Evers <marvin.evers@stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-02mb/google/rex/var/karis: Enhance CNVi and PCIe switchingTyler Wang
1. Set PCIe related GPIOs to NC if fw_config use "WIFI_CNVI". 2. Set CNVi related GPIOs to NC if fw_config use "WIFI_PCIE". 3. Remove "ALC5650_NO_AMP_I2S" case in fw_config_gpio_padbased_override(). bt_i2s_enable_pads should not relevant to audio codec/amp, and it is already enabled in "WIFI_CNVI" case. BUG=b:312099281 TEST=Build and test on karis Change-Id: Ib1a32f1a38ae33cf992b80a3408aa8e2fa3ddab0 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79765 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-31mb/google/nissa/var/craask: Add ILTK touchscreenRen Kuo
Add touchscreen ILTK for craaskwell. Refer to ILI2901A-A200 Data Sheet_V1.1_20231026. BUG=b:308873706 TEST=build and check touchscreen function on craask Change-Id: I6a68855b1659ff0c9cd33a0ec9acbd289f525a3d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79735 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
2023-12-31mb/google/dedede: Create dita variantSheng-Liang Pan
Create the dita variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:317292413 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DITA Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-12-28mb/google/nissa/var/anraggar: add hook for WiFi SAR tablecengjianeng
As a preparation for WiFi SAR table addition, adding hook for it. BRANCH=nissa BUG=b:315418153 TEST=emerge-nissa coreboot Cq-Depend: chrome-internal:6790137 Change-Id: Idb200699bb8c8581b9512ec8ec9442f65f8822b3 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-28mb/pcengines/apu2/mainboard: add/fix comments on PIRQ tableFelix Held
Align the comments on the PIRQ table entries for the PCI bridge devices to the external PCIe ports with the devicetrees of the different APU boards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id25ae8422c7c5c79dc8666a28a8219c77af324da Reviewed-on: https://review.coreboot.org/c/coreboot/+/79676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-28mb/pcengines/apu2/mainboard: improve alignment in PIRQ table entriesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If08f7674509c953cf46c4e0d280edc9f863ef2d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79675 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-28mb/pcengines/apu2/mainboard: add PIRQ routing for 02.4 and 02.5Krystian Hebel
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I30cff76abddd3f9a81ac5041260ca7ab1d5244f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-28mb/google/brox: Add new GFX devicesShelley Chen
Add GFX devices for DDI (eDP and HDMI) and TCP (USC C0 and C2 ports). Copied the PLD placements from USB PLDs. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: Ic39916819f64ede1c80eccfd05ba4916b9f285af Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-26mb/google/myst: Update DXIO descriptor definitionJon Murphy
Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: I23ddd11b7e4da35a0d81299aa648f928e81ea24e Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79626 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-26mb/google/skyrim: Update DXIO descriptor definitionJon Murphy
Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such. BUG=b:281059446 TEST=builds Change-Id: Ic5a06a7d1bdb9123a0a242a571f094ac3233d7b2 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79627 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-26mb/google/zork/dsdt: move LIDS object right after dsdt_top.aslFelix Held
This is a preparation to make the next patch result in identical images for timeless builds and also aligns Zork's DSDT more with Guybrush's DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46835b404be13f150c68680afb3fcc78639e08f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-23mb/hp/snb_ivb_laptops: Add VBT for Elitebook 8460pRiku Viitanen
Extracted from a system running OEM BIOS version F.42. intelvbttool --inlegacy --outvbt data.vbt Change-Id: I6e499eb7ff8edb6556f8211d2fb8246cba5f5276 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79625 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-23mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control,the values before Sensor1 and Sensor2 were set too high. Modify the protection temperature to better meet DUT requirements. BUG=b:291217859 BRANCH=none TEST=emerge-rex coreboot Change-Id: I8abc866c0d05a2437c34198e6b8fb4a58c1cb829 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79683 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-22mb/google/rex/var/karis: Adjust touchscreen power-on sequenceTyler Wang
According to datasheet, EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high should over 5ms. And current measure result is 200us. Set EN_TCHSCR_PWR to output high in bootblock to make it meet datasheet requirment. Measurement result of EN_TCHSCR_PWR high --> SOC_TCHSCR_RST_R_L high: Power on --> 31.7 ms Resume --> 38.7 ms BUG=b:314245238 TEST=Measure the sequence Change-Id: I56e455a980b465f27794b30df058ec0944befc2e Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79571 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22mb/google/nissa/var/gothrax: Add probe for Type-C Port C1 (DB)Yunlong Jia
Add probe DB_C_A_LTE/DB_C_A for Type-C Port C1 (daughter board). DB_A is only used for skus without Type-C Port C1. BUG=b:316048649 TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ifb702c497740953144b43c56653da16fade1053f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79629 Reviewed-by: Kyle Lin <kylelinck@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-22mb/google/brox: Fix config errors with 8 GPIOsShelley Chen
Some GPIOs were not configured correctly according to the HW spreadsheet provided by the HW team. * GPP_B5/GPP_B6 use NF1, not NF2 * GPP_B23 should use NF2, no GPI * GPP_D11 should be set to NC * GPP_E21/22 should be using NF (previous NC) * GPP_F17 is a GPO * GPP_F18 should be an interrupt, not a NF BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I9e1e62adb79bd7fdab935afdbf2d23f9061b88aa Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-22mb/google/brox: Align GPIO reset with HW spreadsheetShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes in this CL are to fix the pad's reset field as needed. See "Intel SoCs" section in https://doc.coreboot.org/getting_started/gpio.html for reset definitions. BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-12-22mb/google/brox: Fix pulls as necessaryShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes in this CL include fixing the pulls for GPIOs as necessary, making sure that it matches what is in the HW team's spreadsheet. BUG=b:300690448 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: Ie50cb3c6fc85f1633c1afd1330c0e040e04b0ec1 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79704 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-22mb/google/brox: Change unused GPIOs to NCShelley Chen
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes here include changing the pad config to NC because it is not being used in ChromeOS. BUG=b:300690448 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I15471e4d7ff25c858b05ef024f15ca7c0b9e598e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79703 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-21mb/google/rex/var/karis: Add HDMI/eDP GPIOs to early GPIO listTyler Wang
Add HDMI GPIO configuration to early GPIO list to support VGA text o/p in Pre-RAM stage on HDMI. BUG=b:316982707 TEST=Erase MRC cache and reboot, SOL text display on HDMI/eDP Change-Id: Idb2af56baeb4d0ef9db5fc1c5dbcebecee6515e6 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79572 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-12-21mb/google/rex/var/screebo: Remove Camera EEPROM off timingWentao Qin
Since the camera sensor and camera eeprom share GPP_A12, remove the off timing to avoid issue of camera sensor loss, but this will increase system power by 5mW. (Before root cause, this is a short term workaround to unblock function test.) BUG=b:298126852 TEST=1. Run coldreboot/warmreboot check see if the camera sensor lost. 2. Run S0ix check to see if the camera function abnormal. Change-Id: I49b6ecbfbf3dddd6575bdaaf9c8fd0ee6c09af25 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79647 Reviewed-by: Jason Z Chen <jason.z.chen@intel.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
2023-12-21mb/google/rex/var/screebo: Configure slew rate to 1/8 for GT domainKun Liu
set slew rate to 1/8 for GT domain. BUG=b:312405633 BRANCH=none TEST=Able to build and boot google/screebo Change-Id: Ib5cb07b7effc4a51c2119183010a03e026f639f8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
2023-12-21mb/google/{brya,brox,rex}: Update ec_sync wake capabilityMark Hasemeyer
Some of the boards use the EC_SYNC pin to wake the AP but do not advertise the pin as wake capable in the CREC _CRS resource. Relevant boards were determined through empirical testing and inspection of gpio configuration. Update the ACPI tables for rex, brya, and brox based boards to advertise their EC_SYNC pin as wake capable. BUG=b:243700486 TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined -Wake Aviko via keypress and verify chromeos-ec as wake source -Wake Screebo via lid open and verify chromeos-ec as wake source Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20mb/amd/onyx_poc/devicetree: enable UART0Felix Held
UART0 is routed to a USB-serial converter chip on the Onyx board, so also enable this UART in the devicetree, so that the OS will be able to use this UART. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b2577d799fd82a0aa0c9b01324930237e204aa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-20mb/google/brox: Enable FSP UPD LpDdrDqDqsReTrainingIvy Jian
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:311450057 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I4a009076e50408a4f7ff16ddc96a0f2e47b09470 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79646 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20mb/google/rex/variants/deku: correct GPIO configurationEran Mitrani
GPP_B02 and GPP_B03 were set incorrectly previously. This CL corrects these settings according to schematics. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id62f15f7a77ac43c72cc6b2645816d6c87133a0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-20mb/google/rex/var/karis: Add PANEL_PWRSEQ_EC_CONTROL in fw_configTyler Wang
Only EC will use field "PANEL_PWRSEQ_EC_CONTROL". Add this field in coreboot for align fw_config settings. BUG=b:314245238 TEST=emerge coreboot pass Change-Id: Icecb44a338ddc28027e362332c6a69cc9fd268d5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79570 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20mb/google/rex/var/karis: Update fw_config FAN fieldTyler Wang
After confirm with thermal, only EC will reference FAN field in fw_config. Update the settings for align fw_config. BUG=b:307822225 TEST=emerge coreboot pass Change-Id: Id7c4cdba29c5500c06d0f2293495650bb14b9e9c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79573 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com>
2023-12-20mb/amd/onyx_poc/devicetree: Enable UART1Varshit Pandya
UART1 is selected for debug uart in Kconfig, it also needs to enabled in devicetree. With this serial output doesn't stop during the device enable step. TEST:Build onyx_poc board Change-Id: I7c910301c6eca5d3057785607139ac03b344bc15 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-20mainboard: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: I602cf024ec84b15b783d36014c725826f9d6595e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79418 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-20mb/google/rex/var/screebo: Configure Acoustic noise mitigationSubrata Banik
Enable Acoustic noise mitigation for google/screebo and set slew rate to 1/8 for IA domain and ignore the slew rate for SA domain. BUG=b:312405633, TEST=Able to build and boot google/screebo. Before: [SPEW ] AcousticNoiseMitigation : 0x0 [SPEW ] FastPkgCRampDisable for Index = 0 : 0x0 [SPEW ] SlowSlewRate for Index = 0 : 0x0 After: [SPEW ] AcousticNoiseMitigation : 0x1 [SPEW ] FastPkgCRampDisable for Index = 0 : 0x1 [SPEW ] SlowSlewRate for Index = 0 : 0x2 Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79323 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-12-20treewide: Use show_notices target for warningsMartin Roth
This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19mb/google/rex/var/screebo: Add delay 1ms after Main 3V3Kun Liu
when S0ix returns S0, PERST needs to delay until Main 3V3 is stable and then pull up BUG=b:313976507 TEST=emerge-rex coreboot,measurement waveform verify pass Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320 Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-19mb/google/nissa/var/anraggar: Use GPP_D15 to control AVDD and AFVDDWeimin Wu
For EVT SCH: 1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera. 2. Delay reset for 5ms when device power on. BUG=b:312663347 TEST=1. Google Camera app working 2. Passed EA verified Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-19mb/google/hatch/var/jinlon: Increase reset deassert delay to 4 msEran Mitrani
With 1ms delay, reset is de-asserted too soon, before power is fully up, causing a glitch to the reset signal. The issue is resolved with 4ms delay. TEST=tested on google/jinlon device and observed the issue is resolved. BUG=b:260253945 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com>
2023-12-18mb/google/rex/var/karis: Enable audio BT offloadTyler Wang
BUG=b:312099281 TEST=Build and boot to Karis. Verify the config from serial logs. w/o this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 0 [SPEW ] BT Interface = 1 ``` w/ this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 1 [SPEW ] BT Interface = 1 ``` Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-17mb/google/nissa/var/anraggar: Disable SDCard controllerWeimin Wu
1. Anraggar doesn't support SDCard, so disable SDCard contorller. 2. Not disabling it will cause can't enter S0ix on first suspend. BUG=b:313585586 TEST=1. check lspci 2. can enter S0ix on first suspend Change-Id: Ie4747d9c5d6ae93d29ef78b629855e0dd320c4db Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-17mb/google/skyrim: Add and use APCB configuration dataMatt DeVillier
This file is identical to the copy currently found in the blobs repository; it is simply being relocated for consistency and since it does not need to be in an external repo. BUG=none TEST=build/boot skyrim Change-Id: I352f58e0d3965356f3282a2653c6c11b44853857 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-17mb/google/guybrush: Add and use APCB configuration dataMatt DeVillier
This file is identical to the copy currently found in the blobs repository; it is simply being relocated for consistency and since it does not need to be in an external repo. BUG=none TEST=build/boot guybrush Change-Id: Ice4cbaccca13e9c4ae246fdcde5c89aa2086f1e1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-17mb/google/zork: Add and use APCB configuration dataMatt DeVillier
This file is identical to the copy currently found in the amd_blobs repository; it is simply being relocated since it is mainboard specific and does not need to be in an external repo. BUG=none TEST=build/boot morphius Change-Id: Ia78fcd065fbf4d5ba6ec4edc3f8f937badf66ecc Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79591 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-17mb/google/brox: Disable EC/PD SW SyncShelley Chen
For initial debugging, we want to disable SW syncing. Will re-enable in the future. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage run gbb_utility --get --flags <image> make sure that it returns 0xa39 Change-Id: I865e9585ab37d1328a0ff54c6343cdad2c02220c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79569 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Short <keithshort@chromium.org>
2023-12-16mb/amd/onyx: rename to onyx_pocVarshit Pandya
Even though this mainboard is called 'Onyx', the openSIL implementation and the corresponding coreboot integration is only a proof of concept that isn't fully featured, has known limitations and bugs, and is not meant for or ready to being productized. Adding the proof of concept suffix to the name should point this out clearly enough so that no potential customer could infer that this might be a fully functional and supported implementation which it is not. Change-Id: I157a8fffdc2a8543465fe8d444ac87f3f417389f Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77896 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>