mb/google/brox: Fix config errors with 8 GPIOs

Some GPIOs were not configured correctly according to the HW
spreadsheet provided by the HW team.
* GPP_B5/GPP_B6 use NF1, not NF2
* GPP_B23 should use NF2, no GPI
* GPP_D11 should be set to NC
* GPP_E21/22 should be using NF (previous NC)
* GPP_F17 is a GPO
* GPP_F18 should be an interrupt, not a NF

BUG=b:300690448,b:316180020
BRANCH=NONE
TEST=emerge-brox coreboot

Change-Id: I9e1e62adb79bd7fdab935afdbf2d23f9061b88aa
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

1 files changed, 11 insertions, 11 deletions

diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 87ea870bcd..7a988e156f 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -95,9 +95,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */
 	PAD_NC(GPP_B4, NONE),
 	/* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */
-	PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF2),
+	PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
 	/* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> ISH_I2C_SENSOR_SCL */
-	PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF2),
+	PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
 	/* GPP_B7 : [NF1: ISH_I2C1_SDA NF2: I2C3_SDA NF6: USB_C_GPP_B7] ==> SOC_I2C3_SDA (NC) */
 	PAD_NC(GPP_B7, NONE),
 	/* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> SOC_I2C3_SCL (NC) */
@@ -120,7 +120,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_B18 : GPP_B18 ==> GPP_B18_STRAP */
 	PAD_NC(GPP_B18, NONE),
 	/* GPP_B23 : SML1ALERT_L/PCHHOT_L ==> PCHHOT_ODL_STRAP */
-	PAD_CFG_GPI(GPP_B23, NONE, PLTRST),
+	PAD_CFG_NF(GPP_B23, NONE, PLTRST, NF2),
 
 	/* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SOC_GPP_C0 (NC) */
 	PAD_NC(GPP_C0, NONE),
@@ -161,8 +161,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
 	/* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C2_LSX_RX_STRAP */
 	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
-	/* GPP_D11 : [] ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* GPP_D11 : [] ==> EN_PP3300_SSD (NC)*/
+	PAD_NC(GPP_D11, NONE),
 	/* GPP_D12 : [NF1: ISH_SPI_MOSI NF2: DDP4_CTRLDATA NF4: TBT_LSX3_RXD NF5: BSSB_LS3_TX NF6: USB_C_GPP_D12 NF7: GSPI2_MOSI] ==> SOC_GPP_D12 (NC) */
 	PAD_NC(GPP_D12, NONE),
 	/* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */
@@ -223,9 +223,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX NF6: USB_C_GPP_E20] ==> SOC_GPP_E20 (NC) */
 	PAD_NC(GPP_E20, NONE),
 	/* GPP_E21 : DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX ==> USB_C1_LSX_RX_STRAP */
-	PAD_NC(GPP_E21, NONE),
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
 	/* GPP_E22 : DDPA_CTRLCLK/DNX_FORCE_RELOAD ==> USB_C0_AUX_DC_STRAP_P */
-	PAD_NC(GPP_E22, NONE),
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
 	/* GPP_E23 : [NF1: DDPA_CTRLDATA] ==> USB_C0_AUX_DC_N */
 	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
 
@@ -262,9 +262,9 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# NF6: USB_C_GPP_F16] ==> PCH_TCHSCR_REPORT_EN */
 	PAD_CFG_GPO(GPP_F16, 0, PLTRST),
 	/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
-	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3),
+	PAD_CFG_GPO(GPP_F17, 1, DEEP),
 	/* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */
-	PAD_CFG_NF(GPP_F18, NONE, PLTRST, NF3),
+	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
 	/* GPP_F19 : SRCCLKREQ6 ==> NC */
 	PAD_NC(GPP_F19, NONE),
 	/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> SOC_GPP_F20 (NC) */
@@ -375,8 +375,8 @@ const struct pad_config *__weak variant_gpio_override_table(size_t *num)
 
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
-	/* GPP_D11 : [] ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_D11, 1, DEEP),
+	/* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */
+	PAD_NC(GPP_D11, NONE),
 	/* GPP_E2  : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */