summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorSean Rhodes <sean@starlabs.systems>2023-12-07 14:43:23 +0000
committerFelix Held <felix-coreboot@felixheld.de>2024-01-11 17:28:02 +0000
commiteed97c538ca6b357ebc5d02be074971d6081c70b (patch)
tree01f82f383dfeb2a7afcfb0ea02abdee1a50ecec6 /src/mainboard
parent590d2d5cd8d5f5fc54d0d1f6783f911bf45a7996 (diff)
mb/starlabs/starbook/rpl: Enable C1e
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3a317d031e71f86afc50b229d1b97197552f4fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 1eaab18938..160656d246 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -5,6 +5,7 @@ chip soc/intel/alderlake
# FSP Silicon
register "eist_enable" = "1"
+ register "enable_c1e" = "1"
register "cnvi_bt_core" = "1"
register "cnvi_bt_audio_offload" = "1"