From eed97c538ca6b357ebc5d02be074971d6081c70b Mon Sep 17 00:00:00 2001
From: Sean Rhodes <sean@starlabs.systems>
Date: Thu, 7 Dec 2023 14:43:23 +0000
Subject: mb/starlabs/starbook/rpl: Enable C1e

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3a317d031e71f86afc50b229d1b97197552f4fa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
---
 src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
index 1eaab18938..160656d246 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
@@ -5,6 +5,7 @@ chip soc/intel/alderlake
 
 	# FSP Silicon
 	register "eist_enable"			= "1"
+	register "enable_c1e"			= "1"
 
 	register "cnvi_bt_core"			= "1"
 	register "cnvi_bt_audio_offload"	= "1"
-- 
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