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path: root/src/mainboard/starlabs/labtop/variants
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2022-06-20mb/starlabs/labtop/kbl: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib5fec81a7a04f2f5ab13784435944601902904d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-20mb/starlabs/labtop/cml: Organise USB ports by hardware portSean Rhodes
Group the USB ports by hardware ports, rather than separate USB 2.0 and 3.0 interfaces. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie9bc6b3e20dddeb14cea195ef9a719432f66c6e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-28mb/starlabs/labtop: Add LabTop Mk IIISean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iii-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ben McMillen <ben@starlabs.systems>
2022-05-26soc/intel/tigerlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the mainboard starlabs/laptop/tgl, since it is obsolete now. Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-26soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the following mainboards, since it is obsolete now. * siemens/chili * starlabs/laptop/cml Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-04-06mb/starlabs/labtop: Remove subsystem device IDSean Rhodes
Remove the subsystem device ID for HDA devices, so that the correct Intel [8086:xxxx] is used. This was an old workaround for Windows that is no longer required with a new driver. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-01mb/starlabs/laptop: Enable rtd3 for SSD on TGLStephen Edworthy
Enabling rtd3 reduces power consumption when the SSD is idle. Tested and verified on the StarBook Mk V (TGL), using PowerTop on Manjaro 21.2.5 GNOME at 20% Brightness. Signed-off-by: Stephen Edworthy <stephen@starlabs.systems> Change-Id: I0d8aa185a322bb8d1aba51ccaab03c521cec2770 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-03-15{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototypeSubrata Banik
This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-08mb/starlabs/labtop: Add LabTop Mk IVSean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iv-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58428 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22mb/starlabs/labtop: Reconfigure GPIOsSean Rhodes
Reconfigure the GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I27ecf066685f2a81ac884a9f276c518544449443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Reconfigure CNVi GPIOsSean Rhodes
Reconfigure the CNVi GPIO's so that they are configured correctly. The original configuration was based on the AMI firmware, and whilst it worked, it wasn't optimal. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Update trackpad GPIO configurationSean Rhodes
Update trackpad GPIO to avoid IRQ Storm, that causes high power consumption when idling or in S3. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22mb/starlabs/labtop: Configure TPM_IRQ GPIO for TGLSean Rhodes
Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the hardware TPM can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756 Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22mb/starlabs/labtop: Don't configure ESPI GPIOsSean Rhodes
Don't configure ESPI GPIOs as the default values are correct. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-15mb/starlabs/labtop: Disconnect unused GPIO'sSean Rhodes
Disconnect all GPIO's that aren't connected to anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2050da62f73c0f99fbfef013c22e35225cc480c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15mb/starlabs/labtop: Add comments for GPIOsSean Rhodes
Add comment for each GPIO details its endpoint based on the schematic. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-01-14soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a81fd58df468e2711108a3243bf116e02986316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-14soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-01-05mb/starlabs/labtop: Remove display from devicetreeSean Rhodes
Remove display from devicetree as Intel's brightness controls are not used on this platform. This solves the below errors appearing in dmesg: No Local Variables are initialized for Method [_BCL] No Arguments are initialized for method [_BCL] Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icf2f2fa33abd11952c888c9502d1d5ef1ad6544f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-05mb/starlabs/labtop: Replace leading whitespace with tabSubrata Banik
Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4d7324148ba182d0317b1f64e39f04a8a55fe79b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-04mb/starlabs/labtop: Enable I2C4Sean Rhodes
Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from configuring anything regarding I2C4 (e.g. GPIOs). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb: Remove dot from end of non-sentence commentPaul Menzel
Run the command below to fix all occurrences. $ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,' Change-Id: I84669341e2c8976953284dbaf113da3397857de3 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb/starlabs/labtop: Update VBTSean Rhodes
Using Vbt.bin version 244, with the following changes: * Add 200ms delay to sink (T3) to avoid no response to AUX Channel transaction, which manifests as a repeating, colourful flicker. * Increase maximum supported refresh rate to 120Hz Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/59727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-20mb/starlabs/labtop: Add enum for `power_profile`Angel Pons
Introduce and use an enum for the `power_profile` CMOS option. Add a helper function that converts CMOS values into enum values. Using an enum allows GCC to warn about switch statements using enum types for their control expressions not handling all possible enum values, and also improves readability. Change-Id: I47a453ea12d164d26908a9944a89a481757e753c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-19mainboard: Fix comment about early GPIOsAngel Pons
These boards program the early GPIO table in bootblock, not romstage. Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15mainboard/starlabs/labtop: Hook up Thunderbolt to CMOSSean Rhodes
Hook up Thunderbolt and related settings to CMOS value of `thunderbolt`. Changes TcssXhciEn, UsbTcPortEn and the relevant PCI devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/starlabs/labtop: Enable SMBus in Device TreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22mainboard/starlabs: Add StarBook Mk VSean Rhodes
Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56088 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04Revert "src/mainboard: Add Star Labs labtop series"Tim Wawrzynczak
This reverts commit 2e665eb8daa2963c52092e694a5316dc544a23f5. Reason for revert: Was submitted too early and out-of-order. Change-Id: I119b7a81b849bbe3424d73d5fdf9b55481444686 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54971 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04src/mainboard: Add Star Labs labtop seriesSean Rhodes
Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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