mainboard/starlabs: Add StarBook Mk V

Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/starbook-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I090971a9e8d2be5b08be886d00d304607304b645
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56088
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 791 insertions, 0 deletions

diff --git a/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc
new file mode 100644
index 0000000000..2a505c35c7
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/tgl/Makefile.inc
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += romstage.c
+
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/board.fmd b/src/mainboard/starlabs/labtop/variants/tgl/board.fmd
new file mode 100644
index 0000000000..932739e1e4
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/tgl/board.fmd
@@ -0,0 +1,18 @@
+#
+# Manually defined FMD in order to ensure that space is reserved for the EC
+# at the top of the BIOS region.
+#
+FLASH@0xff000000 0x1000000 {
+	SI_ALL@0x0 0x500000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000
+	}
+	SI_BIOS@0x500000 0xB00000 {
+		EC@0x0 0x20000
+		RW_MRC_CACHE@0x20000 0x10000
+		SMMSTORE@0x30000 0x40000
+		CONSOLE@0x70000 0x20000
+		FMAP@0x90000 0x800
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/data.vbt b/src/mainboard/starlabs/labtop/variants/tgl/data.vbt
new file mode 100644
index 0000000000..67dc497090
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/tgl/data.vbt
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
new file mode 100644
index 0000000000..5c55dce396
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
@@ -0,0 +1,240 @@
+chip soc/intel/tigerlake
+# CPU
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable"			= "1"
+
+	# Graphics
+	# IGD Displays
+	register "gfx"				= "GMA_STATIC_DISPLAYS(0)"
+	# Not used but timings left for reference
+	# register "panel_cfg" = "{
+	#	.up_delay_ms			=  0,				// T3
+	#	.backlight_on_delay_ms		=  0,				// T7
+	#	.backlight_off_delay_ms		=  50,				// T9
+	#	.down_delay_ms			=  0,				// T10
+	#	.cycle_delay_ms			=  500,				// T12
+	#	.backlight_pwm_hz		=  200,				// PWM
+	# }"
+
+	# FSP Memory
+	register "CnviBtCore"			= "true"
+	register "CnviBtAudioOffload"		= "1"
+	register "enable_c6dram"		= "1"
+	register "HeciEnabled"			= "1"
+	register "SaGv"				= "SaGv_Enabled"
+        register "TcssD3ColdDisable"		= "1"
+
+	# FSP Silicon
+	# Serial I/O
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART2]		= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "PchPmSlpS3MinAssert"		= "2"				# 50ms
+	register "PchPmSlpS4MinAssert"		= "3"				# 1s
+	register "PchPmSlpSusMinAssert"		= "3"				# 500ms
+	register "PchPmSlpAMinAssert"		= "3"				# 2s
+
+	# Thermal
+	register "tcc_offset"			= "10"
+
+	# PM Util
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "pmc_gpe0_dw0"			= "GPP_B"
+	register "pmc_gpe0_dw1"			= "GPP_C"
+	register "pmc_gpe0_dw2"			= "GPP_E"
+
+	# Enable the correct decode ranges on the LPC bus.
+	register "lpc_ioe"			= "LPC_IOE_EC_4E_4F |
+						   LPC_IOE_SUPERIO_2E_2F |
+						   LPC_IOE_KBC_60_64 |
+						   LPC_IOE_EC_62_66 |
+						   LPC_IOE_LGE_200"
+
+	# PCIe Clock
+	register "PcieClkSrcClkReq[0]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]"		= "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[6]"		= "PCIE_CLK_NOTUSED"
+
+# Actual device tree.
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end						# Host Bridge
+		device pci 02.0 on  end						# Integrated Graphics Device
+		device pci 04.0 on						# SA Thermal Device
+			register "Device4Enable"		= "1"
+		end
+		device pci 05.0 off end						# IPU
+		device pci 06.0 off end						# PEG60
+		device pci 07.0 on  end						# TBT_PCIe0
+		device pci 07.1 off end						# TBT_PCIe1
+		device pci 07.2 off end						# TBT_PCIe2
+		device pci 07.3 off end						# TBT_PCIe3
+		device pci 08.0 on  end						# Gaussian Mixture Model
+		device pci 09.0 off end						# NPK
+		device pci 0a.0 off end						# Crash-log SRAM
+		device pci 0d.0 on						# USB xHCI
+			register "UsbTcPortEn"			= "1"
+			register "TcssXhciEn"			= "1"
+			register "TcssAuxOri"			= "0"
+		end
+		device pci 0d.1 off end						# USB xDCI (OTG)
+		device pci 0d.2 on						# TBT DMA0
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio"	= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device pci 0d.3 off end						# TBT
+		device pci 0e.0 off end						# VMD
+		device pci 10.6 off end
+		device pci 10.7 off end
+		device pci 12.0 off end						# Thermal Subsystem
+		device pci 12.6 off end						# GSPI #2
+		device pci 14.0 on						# USB xHCI
+			### USB 2.0 Devices
+			# Motherboard USB Type C
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Webcam
+			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard SD Card
+			register "usb2_ports[5]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Bluetooth
+			register "usb2_ports[9]"		= "USB2_PORT_MID(OC_SKIP)"
+
+			### USB 3.0 Devices
+			# Motherboard USB Type C
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			### Thunderbolt 4.0 Devices
+			# Motherboard Thunderbolt 4.0
+			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
+		end
+		device pci 14.1 off end						# USB xDCI (OTG)
+		device pci 14.2 on  end						# USB xDCI (OTG)
+		device pci 14.3 on						# CNVi
+			chip drivers/wifi/generic
+				register "wake"			= "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device pci 15.0 on						# I2C0
+			chip drivers/i2c/hid
+				register "generic.hid"		= ""STAR0001""
+				register "generic.desc"		= ""Touchpad""
+				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_C8_IRQ)"
+				register "generic.probed"	= "1"
+				register "hid_desc_reg_offset"	= "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 off end						# I2C1
+		device pci 15.2 off end						# I2C2
+		device pci 15.3 off end						# I2C3
+		device pci 16.0 on  end						# Management Engine Interface 1
+		device pci 16.1 off end						# Management Engine Interface 2
+		device pci 16.2 off end						# Management Engine IDE-R
+		device pci 16.3 off end						# Management Engine KT Redirection
+		device pci 16.4 off end						# Management Engine Interface 3
+		device pci 16.5 off end						# Management Engine Interface 4
+		device pci 17.0 on						# SATA
+			register "SataSalpSupport"		= "1"
+			# Port 1
+			register "SataPortsEnable[1]"		= "1"
+			register "SataPortsDevSlp[1]"		= "1"
+		end
+		device pci 19.0 off end						# I2C4
+		device pci 19.1 off end						# I2C5
+		device pci 19.2 on  end						# UART #2
+		device pci 1c.0 off end						# PCI Express Port 1
+		device pci 1c.1 off end						# PCI Express Port 2
+		device pci 1c.2 off end						# PCI Express Port 3
+		device pci 1c.3 off end						# PCI Express Port 4
+		device pci 1c.4 off end						# PCI Express Port 5
+		device pci 1c.5 off end						# PCI Express Port 6
+		device pci 1c.6 off end						# PCI Express Port 7
+		device pci 1c.7 off end						# PCI Express Port 8
+		device pci 1d.0 on						# PCI Express Port 9 (SSD x4)
+			register "HybridStorageMode"		= "0"
+			register "PcieRpEnable[8]"		= "1"
+			register "PcieRpLtrEnable[8]"		= "1"
+			register "PcieClkSrcUsage[3]"		= "0x08"
+			register "PcieClkSrcClkReq[3]"		= "3"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off end						# PCI Express Port 10
+		device pci 1d.2 off end						# PCI Express Port 11
+		device pci 1d.3 off end						# PCI Express Port 12
+		device pci 1e.0 off end						# UART #0
+		device pci 1e.1 off end						# UART #1
+		device pci 1e.2 off end						# GSPI #0
+		device pci 1e.3 on  end						# GSPI #1
+		device pci 1f.0 on						# LPC Interface
+			register "gen1_dec"			= "0x000c1641"
+			register "gen2_dec"			= "0x000c0681"
+			register "gen3_dec"			= "0x000c0081"
+
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+                        end
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.00 on  end			# IO Interface
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 on				# PS/2 Keyboard
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
+				end
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device pci 1f.1 off end						# P2SB
+		device pci 1f.2 hidden end					# Power Management Controller
+		device pci 1f.3 on						# Intel HDA
+			subsystemid 0x10ec 0x1200
+			register "PchHdaAudioLinkHdaEnable"	= "1"
+		end
+		device pci 1f.4 on  end						# SMBus
+		device pci 1f.5 on  end						# PCH SPI
+		device pci 1f.6 off end						# GbE
+		device pci 1f.7 off end						# TH
+	end
+end
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devtree.c b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c
new file mode 100644
index 0000000000..034877c66e
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devtree.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <option.h>
+#include <types.h>
+#include <variants.h>
+
+void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+
+	struct soc_power_limits_config *soc_conf_2core =
+		&cfg->power_limits_config[POWER_LIMITS_U_2_CORE];
+
+	struct soc_power_limits_config *soc_conf_4core =
+		&cfg->power_limits_config[POWER_LIMITS_U_4_CORE];
+
+	struct device *nic_dev = pcidev_on_root(0x14, 3);
+
+	/* Update PL1 & PL2 based on CMOS settings */
+	switch (get_uint_option("power_profile", 0)) {
+	case 1:
+		soc_conf_2core->tdp_pl1_override = 15;
+		soc_conf_4core->tdp_pl1_override = 15;
+		soc_conf_2core->tdp_pl2_override = 25;
+		soc_conf_4core->tdp_pl2_override = 25;
+		break;
+	case 2:
+		soc_conf_2core->tdp_pl1_override = 28;
+		soc_conf_4core->tdp_pl1_override = 28;
+		soc_conf_2core->tdp_pl2_override = 40;
+		soc_conf_4core->tdp_pl2_override = 40;
+		break;
+	default:
+		disable_turbo();
+		soc_conf_2core->tdp_pl1_override = 15;
+		soc_conf_4core->tdp_pl1_override = 15;
+		soc_conf_2core->tdp_pl2_override = 15;
+		soc_conf_4core->tdp_pl2_override = 15;
+		break;
+	}
+
+	/* Enable/Disable Wireless based on CMOS settings */
+	if (get_uint_option("wireless", 1) == 0)
+		nic_dev->enabled = 0;
+
+	/* Enable/Disable Webcam based on CMOS settings */
+	if (get_uint_option("webcam", 1) == 0)
+		cfg->usb2_ports[3].enable = 0;
+}
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/gpio.c b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c
new file mode 100644
index 0000000000..a541c0724b
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/tgl/gpio.c
@@ -0,0 +1,224 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variants.h>
+
+/*
+ * All definitions are taken from a comparison of the output of "inteltool -a"
+ * using the stock BIOS and with coreboot.
+ */
+
+/* Early pad configuration in romstage. */
+const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage.c */
+const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD11, 0, PWROK),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	PAD_NC(GPP_A7, NONE),
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
+	PAD_NC(GPP_A10, NONE),
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1),
+	PAD_NC(GPP_A13, NONE),
+	PAD_CFG_GPO(GPP_A14, 0, PLTRST),
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_NC(GPP_A22, NONE),
+	PAD_CFG_GPO(GPP_A23, 0, PLTRST),
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_NC(GPP_B2, NONE),
+	PAD_NC(GPP_B3, NONE),
+	PAD_NC(GPP_B4, NONE),
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_CFG_GPO(GPP_B17, 0, PWROK),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 0, DEEP),
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	PAD_NC(GPP_C9, NONE),
+	PAD_CFG_GPO(GPP_C10, 0, PWROK),
+	PAD_CFG_GPO(GPP_C11, 0, PWROK),
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C13, 1, PLTRST),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+	PAD_NC(GPP_D4, NONE),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	PAD_NC(GPP_D9, NATIVE),
+	PAD_NC(GPP_D10, NATIVE),
+	PAD_NC(GPP_D11, NATIVE),
+	PAD_NC(GPP_D12, NATIVE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+	PAD_CFG_GPI(GPP_D18, NONE, DEEP),
+	PAD_CFG_TERM_GPO(GPP_D19, 1, UP_20K, DEEP),
+	PAD_NC(GPP_E0, NONE),
+	PAD_NC(GPP_E1, NONE),
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
+	PAD_NC(GPP_E4, NONE),
+	PAD_NC(GPP_E5, NONE),
+	PAD_NC(GPP_E6, NONE),
+	PAD_NC(GPP_E7, NONE),
+	PAD_NC(GPP_E8, NONE),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_NC(GPP_E10, NONE),
+	PAD_NC(GPP_E11, NONE),
+	PAD_NC(GPP_E12, NONE),
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NATIVE),
+	PAD_NC(GPP_E19, NATIVE),
+	PAD_NC(GPP_E20, NATIVE),
+	PAD_NC(GPP_E21, NATIVE),
+	PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF2),
+	PAD_CFG_GPO(GPP_E23, 0, DEEP),
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	PAD_NC(GPP_F6, NONE),
+	PAD_CFG_GPO(GPP_F7, 1, PLTRST),
+	PAD_NC(GPP_F8, NONE),
+	PAD_CFG_GPO(GPP_F9, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_NC(GPP_F17, NONE),
+	PAD_NC(GPP_F18, NONE),
+	PAD_NC(GPP_F19, NONE),
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+	PAD_CFG_GPO(GPP_H0, 0, DEEP),
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	PAD_CFG_GPO(GPP_H2, 0, DEEP),
+	PAD_NC(GPP_H3, NONE),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_CFG_GPO(GPP_H14, 1, PLTRST),
+	PAD_NC(GPP_H15, NONE),
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	PAD_NC(GPP_H19, NONE),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_R5, 0, PLTRST),
+	PAD_CFG_GPO(GPP_R6, 1, PLTRST),
+	PAD_NC(GPP_R7, NONE),
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+	PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2),
+	PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2),
+	PAD_NC(GPP_U4, NONE),
+	PAD_NC(GPP_U5, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c b/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c
new file mode 100644
index 0000000000..7903d96259
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/tgl/hda_verb.c
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
+	0x10ec1200, /* Subsystem ID */
+	38,	    /* Number of jacks (NID entries) */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID: 0x10EC1200 */
+	AZALIA_SUBVENDOR(0, 0x10ec1200),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x04ab1020),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x40700001),
+	AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x042b1010),
+
+	/* Reset to D0 */
+	0x00170500,
+	0x00170500,
+	0x00170500,
+	0x00170500,
+
+	/* Reset Register */
+	0x0205001A,
+	0x02048003,
+	0x0205001A,
+	0x0204C003,
+
+	/* ALC256 Default 1 */
+	0x0205003C,
+	0x02040354,
+	0x0205003C,
+	0x02040314,
+
+	/* ALC256 Default 2 */
+	0x02050040,
+	0x02049800,
+	0x02050034,
+	0x0204023C,
+
+	/* ALC256 Default 3 */
+	0x05750003,
+	0x05740DA3,
+	0x02050046,
+	0x02040004,
+
+	/* ALC256 Default 4 */
+	0x0205001B,
+	0x02040A4B,
+	0x02050008,
+	0x02046A6C,
+
+	/* Jack Detection */
+	0x02050009,
+	0x0204E003,
+	0x0205000A,
+	0x02047770,
+
+	/* Combo Jack TRS setting */
+	0x02050038,
+	0x02047901,
+
+	/* Disable Microphone Security */
+	0x0205000D,
+	0x0204A020,
+
+	/* Enable ADC clock */
+	0x02050005,
+	0x02040700,
+
+	/* Speaker Enable */
+	0x0205000C,
+	0x020401EF,
+
+	/*
+	 * Equalizer:
+	 *
+	 * AGC
+	 * Threshold:	- 6.00 dB
+	 * Front Boost:	+ 6.00 dB
+	 * Post Boost:	+ 6.00 dB
+	 *
+	 * Low Pass Filter
+	 * Boost Gain:	Enabled
+	 * BW:		200Hz
+	 * Gain:	+ 4.00 dB
+	 *
+	 * Band Pass Filter 1
+	 * Fc:		240Hz
+	 * BW:		400Hz
+	 * Gain:	- 4.00 dB
+	 *
+	 * Band Pass Filter 2
+	 * Fc:		16000Hz
+	 * BW:		1000Hz
+	 * Gain:	+ 12.00 dB
+	 *
+	 * High Pass Filter
+	 * Boost Gain:	Enabled
+	 * BW:		200Hz
+	 * Gain:	- 4.00 dB
+	 *
+	 * Class D Amp
+	 * Power:	2.5W
+	 * Resistance:	4ohms
+	 *
+	 * EQ Output
+	 * Left:	+ 0.00 dB
+	 * Right:	+ 0.00 dB
+	 *
+	 * VARQ
+	 * Q:		0.707
+	 */
+
+	0x05350000,
+	0x053404DA,
+	0x0535001d,
+	0x05340800,
+
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341F7A,
+
+	0x05350004,
+	0x0534FA18,
+	0x0535000F,
+	0x0534C295,
+
+	0x05350010,
+	0x05341D73,
+	0x05350011,
+	0x0534FA18,
+
+	0x05350012,
+	0x05341E08,
+	0x05350013,
+	0x05341C10,
+
+	0x05350014,
+	0x05342FB2,
+	0x0535001B,
+	0x05341F2C,
+
+	0x0535001C,
+	0x0534095C,
+	0x05450000,
+	0x05440000,
+
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+
+	0x05450003,
+	0x05441F7A,
+	0x05450004,
+	0x0544FA18,
+
+	0x0545000F,
+	0x0544C295,
+	0x05450010,
+	0x05441D73,
+
+	0x05450011,
+	0x0544FA18,
+	0x05450012,
+	0x05441E08,
+
+	0x05450013,
+	0x05441C10,
+	0x05450014,
+	0x05442FB2,
+
+	0x0545001B,
+	0x05441F2C,
+	0x0545001C,
+	0x0544095C,
+
+	0x05350000,
+	0x0534C4DA,
+	0x02050038,
+	0x02044901,
+
+	0x02050013,
+	0x0204422F,
+	0x02050016,
+	0x02044E50,
+
+	0x02050012,
+	0x0204EBC4,
+	0x02050020,
+	0x020451FF,
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c
new file mode 100644
index 0000000000..dae2142a91
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <types.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg mem_config = {
+		.type = MEM_TYPE_DDR4,
+	};
+
+	const bool half_populated = false;
+
+	const struct mem_spd ddr4_spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+			},
+			[1] = {
+				.addr_dimm[0] = 0x52,
+			},
+		},
+	};
+
+	memcfg_init(&mupd->FspmConfig, &mem_config, &ddr4_spd_info, half_populated);
+
+	const uint8_t vtd = get_uint_option("vtd", 1);
+		mupd->FspmConfig.VtdDisable = !vtd;
+
+	const uint8_t ht = get_uint_option("hyper_threading",
+		mupd->FspmConfig.HyperThreading);
+	mupd->FspmConfig.HyperThreading = ht;
+};