mb/starlabs/labtop: Add LabTop Mk III

Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/labtop-mk-iii-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ben McMillen <ben@starlabs.systems>

9 files changed, 850 insertions, 0 deletions

diff --git a/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc
new file mode 100644
index 0000000000..2a505c35c7
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc
@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += romstage.c
+
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/board.fmd b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd
new file mode 100644
index 0000000000..ef63457460
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/board.fmd
@@ -0,0 +1,9 @@
+FLASH 8M {
+	BIOS@0x200000 0x600000 {
+		RW_MRC_CACHE@0x0 0x10000
+		SMMSTORE@0x10000 0x40000
+		CONSOLE@0x50000 0x20000
+		FMAP@0x70000 0x200
+		COREBOOT(CBFS)
+	}
+}
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/data.vbt b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt
new file mode 100644
index 0000000000..12010f3542
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/data.vbt
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb
new file mode 100644
index 0000000000..5c2c66aca0
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb
@@ -0,0 +1,184 @@
+chip soc/intel/skylake
+# CPU
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable"			= "1"
+
+	# Graphics
+	# IGD Displays
+	register "panel_cfg" = "{
+		.up_delay_ms			=  0,				// T3
+		.backlight_on_delay_ms		=  0,				// T7
+		.backlight_off_delay_ms		=  0,				// T9
+		.down_delay_ms			=  0,				// T10
+		.cycle_delay_ms			=  500,				// T12
+		.backlight_pwm_hz		=  200,				// PWM
+	}"
+
+	# FSP Memory
+	register "SaGv"				= "SaGv_Enabled"
+
+# FSP Silicon
+	# Serial I/O
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]		= PchSerialIoPci,
+		[PchSerialIoIndexUart2]		= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "PmConfigSlpS3MinAssert"	= "2"				# 50ms
+	register "PmConfigSlpS4MinAssert"	= "3"				# 1s
+	register "PmConfigSlpSusMinAssert"	= "3"				# 500ms
+	register "PmConfigSlpAMinAssert"	= "3"				# 2s
+
+	# Thermal
+	register "tcc_offset"			= "10"
+
+	# PM Util
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	register "gpe0_dw0"			= "GPP_B"
+	register "gpe0_dw1"			= "GPP_C"
+	register "gpe0_dw2"			= "GPP_E"
+
+	# Enable the correct decode ranges on the LPC bus.
+	register "lpc_ioe"			= "LPC_IOE_EC_4E_4F |
+						   LPC_IOE_KBC_60_64 |
+						   LPC_IOE_EC_62_66"
+
+# Actual device tree.
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on  end						# Host Bridge
+		device pci 02.0 on  end						# Integrated Graphics Device
+		device pci 04.0 on  end						# SA Thermal Device
+		device pci 14.0 on						# USB xHCI
+			### USB 2.0 Devices
+			# Motherboard USB Type C
+			register "usb2_ports[0]"		= "USB2_PORT_TYPE_C(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Webcam
+			register "usb2_ports[3]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Internal Bluetooth
+			register "usb2_ports[5]"		= "USB2_PORT_MID(OC_SKIP)"
+			# Daughterboard SD Card
+			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
+
+			### USB 3.0 Devices
+			# Motherboard USB Type C
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Motherboard USB 3.0
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+			# Daughterboard USB 3.0
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+		end
+		device pci 14.1 off end						# USB xDCI (OTG)
+		device pci 14.2 on  end						# Thermal Subsystem
+		device pci 15.0 on						# I2C #0
+			chip drivers/i2c/hid
+				register "generic.hid"		= ""STAR0001""
+				register "generic.desc"		= ""Touchpad""
+				register "generic.irq"		= "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
+				register "generic.probed"	= "1"
+				register "hid_desc_reg_offset"	= "0x20"
+				device i2c 2c on end
+			end
+		end
+		device pci 15.1 off end						# I2C1
+		device pci 15.2 off end						# I2C2
+		device pci 15.3 off end						# I2C3
+		device pci 16.0 on  end						# Management Engine Interface 1
+		device pci 16.1 off end						# Management Engine Interface 2
+		device pci 16.2 off end						# Management Engine IDE-R
+		device pci 16.3 off end						# Management Engine KT Redirection
+		device pci 16.4 off end						# Management Engine Interface 3
+		device pci 17.0 on						# SATA
+			register "SataSalpSupport"		= "1"
+			# Port 1
+			register "SataPortsEnable[1]"		= "1"
+			register "SataPortsDevSlp[1]"		= "1"
+		end
+		device pci 19.0 on  end						# UART #2
+		device pci 19.1 off end						# I2C4
+		device pci 19.2 off end						# I2C5
+		device pci 1c.0 off end						# PCI Express Port 1
+		device pci 1c.1 off end						# PCI Express Port 2
+		device pci 1c.2 off end						# PCI Express Port 3
+		device pci 1c.3 off end						# PCI Express Port 4
+		device pci 1c.4 off end						# PCI Express Port 5
+		device pci 1c.5 on						# PCI Express Port 6
+			register "PcieRpEnable[5]"		= "1"
+			register "PcieRpClkReqSupport[5]"	= "1"
+			register "PcieRpClkReqNumber[5]"	= "4"
+			register "PcieRpClkSrcNumber[5]"	= "4"
+			register "PcieRpLtrEnable[5]"		= "1"
+			chip drivers/wifi/generic
+				device generic 0 on end
+			end
+		end
+		device pci 1c.6 off end						# PCI Express Port 7
+		device pci 1c.7 off end						# PCI Express Port 8
+		device pci 1d.0 on						# PCI Express Port 9(SSD x4)
+			register "PcieRpEnable[8]"		= "1"
+			register "PcieRpClkReqSupport[8]"	= "1"
+			register "PcieRpClkReqNumber[8]"	= "0"
+			register "PcieRpClkSrcNumber[8]"	= "0"
+			register "PcieRpLtrEnable[8]"		= "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off end						# PCI Express Port 10
+		device pci 1d.2 off end						# PCI Express Port 11
+		device pci 1d.3 off end						# PCI Express Port 12
+		device pci 1e.0 on  end						# UART #0
+		device pci 1e.1 off end						# UART #1
+		device pci 1e.2 off end						# GSPI #0
+		device pci 1e.3 off end						# GSPI #1
+		device pci 1e.4 off end						# eMMC
+		device pci 1e.5 off end						# SDIO
+		device pci 1e.6 off end						# SDCard
+		device pci 1f.0 on						# LPC Interface
+			register "gen1_dec"			= "0x000c0681"
+			register "gen2_dec"			= "0x000c1641"
+			register "gen3_dec"			= "0x00000069"
+			register "gen4_dec"			= "0x0000006d"
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.00 on  end			# IO Interface
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 on				# PS/2 Keyboard
+					io 0x60			= 0x0060
+					io 0x62			= 0x0064
+					irq 0x70		= 1
+				end
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device pci 1f.1 off end						# P2SB
+		device pci 1f.2 on  end						# Power Management Controller
+		device pci 1f.3 on  end						# Intel HDA
+		device pci 1f.4 on  end						# SMBus
+		device pci 1f.5 on  end						# PCH SPI
+		device pci 1f.6 off end						# GbE
+	end
+end
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/devtree.c b/src/mainboard/starlabs/labtop/variants/kbl/devtree.c
new file mode 100644
index 0000000000..566b0328e7
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/devtree.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <option.h>
+#include <types.h>
+#include <variants.h>
+
+void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+
+	struct soc_power_limits_config *soc_conf = &cfg->power_limits_config;
+
+	struct device *nic_dev = pcidev_on_root(0x1c, 5);
+
+	/* Update PL1 & PL2 based on CMOS settings */
+	switch (get_uint_option("power_profile", 0)) {
+	case 1:
+		soc_conf->tdp_pl1_override = 17;
+		soc_conf->tdp_pl2_override = 20;
+		break;
+	case 2:
+		soc_conf->tdp_pl1_override = 20;
+		soc_conf->tdp_pl2_override = 25;
+		break;
+	default:
+		disable_turbo();
+		soc_conf->tdp_pl1_override = 15;
+		soc_conf->tdp_pl2_override = 15;
+		break;
+	}
+
+	/* Enable/Disable Wireless based on CMOS settings */
+	if (get_uint_option("wireless", 1) == 0)
+		nic_dev->enabled = 0;
+
+	/* Enable/Disable Webcam based on CMOS settings */
+	if (get_uint_option("webcam", 1) == 0)
+		cfg->usb2_ports[3].enable = 0;
+}
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads
new file mode 100644
index 0000000000..8402b39a94
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,   -- USB-C
+      HDMI1, -- USB-C
+      HDMI2, -- HDMI
+      eDP,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/gpio.c b/src/mainboard/starlabs/labtop/variants/kbl/gpio.c
new file mode 100644
index 0000000000..9ab74148da
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/gpio.c
@@ -0,0 +1,356 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variants.h>
+
+/*
+ * All definitions are taken from a comparison of the output of "inteltool -a"
+ * using the stock BIOS and with coreboot.
+ */
+
+/* Early pad configuration in bootblock. */
+const struct pad_config early_gpio_table[] = {
+	/* C20:	 UART2_RXD			*/
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+	/* C21:	 UART2_TXD			*/
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage. */
+const struct pad_config gpio_table[] = {
+	/* GPD0:	PM_BATLOW_N		*/
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	/* GPD1:	AC_PRESENT		*/
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	/* GPD2:	Not Connected		*/
+	PAD_NC(GPD2, NONE),
+	/* GPD3:	SOC_PWRBTN_N		*/
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	/* GPD4:	SLP_S3_N		*/
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	/* GPD5:	SLP_S4_N		*/
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	/* GPD6:	Not Connected		*/
+	PAD_NC(GPD6, NONE),
+	/* GPD7:	Not Connected		*/
+	PAD_NC(GPD7, NONE),
+	/* GPD8:	SUS_CLK			*/
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	/* GPD9:	Not Connected		*/
+	PAD_NC(GPD9, NONE),
+	/* GPD10:	Not Connected		*/
+	PAD_NC(GPD10, NONE),
+	/* GPD11:	Not Connected		*/
+	PAD_NC(GPD11, NONE),
+	/* GPP_A0:	KBRST_N			*/
+	PAD_NC(GPP_A0, NONE),
+	/* GPP_A1:	LDC_AD0			*/
+	PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+	/* GPP_A2:	LPC_AD1			*/
+	PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+	/* GPP_A3:	LDC_AD2			*/
+	PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+	/* GPP_A4:	LDC_AD3			*/
+	PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+	/* GPP_A5:	LPC_FRAME_N		*/
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+	/* GPP_A6:	LPC_SERIRQ		*/
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+	/* GPP_A7:	Not Connected		*/
+	PAD_NC(GPP_A7, NONE),
+	/* GPP_A8:	PM_CLKRUN_N		*/
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+	/* GPP_A9:	LPC_CLK_EC		*/
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	/* GPP_A10:	LPC_CLK_Debug		*/
+	PAD_NC(GPP_A10, DN_20K),
+	/* GPP_A11:	PME_N			*/
+	PAD_CFG_GPI(GPP_A11, DN_20K, DEEP),
+	/* GPP_A12:	Not Connected		*/
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_A13:	SUSPWRDNACK		*/
+	PAD_NC(GPP_A13, DN_20K),
+	/* GPP_A14:	PM_SUS_STAT_N		*/
+	PAD_NC(GPP_A14, DN_20K),
+	/* GPP_A15:	SUSACK#			*/
+	PAD_NC(GPP_A15, DN_20K),
+	/* GPP_A16:	Not Connected		*/
+	PAD_NC(GPP_A16, DN_20K),
+	/* GPP_A17:	Not Connected		*/
+	PAD_NC(GPP_A17, DN_20K),
+	/* GPP_A18:	Not Connected		*/
+	PAD_NC(GPP_A18, DN_20K),
+	/* GPP_A19:	Not Connected		*/
+	PAD_NC(GPP_A19, DN_20K),
+	/* GPP_A20:	Not Connected		*/
+	PAD_NC(GPP_A20, NONE),
+	/* GPP_A21:	Not Connected		*/
+	PAD_NC(GPP_A21, DN_20K),
+	/* GPP_A22:	FP_SSP0_INT		*/
+	PAD_NC(GPP_A22, DN_20K),
+	/* GPP_A23:	FP_SSP0_RST		*/
+	PAD_NC(GPP_A23, DN_20K),
+	/* GPP_B0:	Not Connected		*/
+	PAD_NC(GPP_B0, DN_20K),
+	/* GPP_B1:	Not Connected		*/
+	PAD_NC(GPP_B1, DN_20K),
+	/* GPP_B2:	+V3P3A_PCH		*/
+	PAD_NC(GPP_B2, DN_20K),
+	/* GPP_B3:	Not Connected		*/
+	PAD_NC(GPP_B3, DN_20K),
+	/* GPP_B4:	BT_OFF_N_MCP		*/
+	PAD_CFG_TERM_GPO(GPP_B4, 1, UP_20K, DEEP),
+	/* GPP_B5:	SRCCLKREQ0#		*/
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+	/* GPP_B6:	CLKREQ1#		*/
+	PAD_CFG_GPI(GPP_B6, DN_20K, DEEP),
+	/* GPP_B7:	CLKREQ2#		*/
+	PAD_CFG_NF(GPP_B7, DN_20K, DEEP, NF1),
+	/* GPP_B8:	CLKREQ3#		*/
+	PAD_CFG_NF(GPP_B8, DN_20K, DEEP, NF1),
+	/* GPP_B9:	WLAN_CLKREQ#		*/
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	/* GPP_B10:	CLKREQ5#		*/
+	PAD_CFG_NF(GPP_B10, DN_20K, DEEP, NF1),
+	/* GPP_B11:	Not Connected		*/
+	PAD_NC(GPP_B11, DN_20K),
+	/* GPP_B12	SLP_S0_N		*/
+	PAD_NC(GPP_B12, DN_20K),
+	/* GPP_B13:	SYS_RESET#		*/
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* GPP_B14:	HDA_SPKR		*/
+	PAD_NC(GPP_B14, DN_20K),
+	/* GPP_B15:	Not Connected		*/
+	PAD_NC(GPP_B15, DN_20K),
+	/* GPP_B16:	Not Connected		*/
+	PAD_NC(GPP_B16, DN_20K),
+	/* GPP_B17:	Not Connected		*/
+	PAD_NC(GPP_B17, DN_20K),
+	/* GPP_B18:	+V3P3A_PCH		*/
+	PAD_NC(GPP_B18, DN_20K),
+	/* GPP_B19:	FP_SSP0_CS		*/
+	PAD_NC(GPP_B19, DN_20K),
+	/* GPP_B20:	FP_SSP0_CLK		*/
+	PAD_NC(GPP_B20, DN_20K),
+	/* GPP_21:	FP_SSP0_MISO		*/
+	PAD_NC(GPP_B21, DN_20K),
+	/* GPP_22:	FP_SSP0_MOSI		*/
+	PAD_NC(GPP_B22, DN_20K),
+	/* GPP_B23:	SML1ALERT#/PCHHOT#	*/
+	PAD_NC(GPP_B23, DN_20K),
+	/*GPP_C0:	SMBCLK			*/
+	PAD_CFG_NF(GPP_C0, UP_20K, DEEP, NF1),
+	/* GPP_C1:	SMBDATA			*/
+	PAD_CFG_NF(GPP_C1, UP_20K, DEEP, NF1),
+	/* GPP_C2:	SMBALERT#		*/
+	PAD_NC(GPP_C2, DN_20K),
+	/* GPP_C3:	SML0CLK			*/
+	PAD_NC(GPP_C3, DN_20K),
+	/* GPP_C4:	SML0DATA		*/
+	PAD_NC(GPP_C4, DN_20K),
+	/* GPP_C5:	SML0ALERT#		*/
+	PAD_NC(GPP_C5, DN_20K),
+	/* GPP_C6:	SML1CLK			*/
+	PAD_NC(GPP_C6, DN_20K),
+	/* GPP_C7:	SML1DATA		*/
+	PAD_NC(GPP_C7, DN_20K),
+	/* GPP_C8:	UART0_RXD		*/
+	PAD_CFG_NF(GPP_C8, UP_20K, DEEP, NF1),
+	/* GPP_C9:	UART0_TXD		*/
+	PAD_CFG_NF(GPP_C9, UP_20K, DEEP, NF1),
+	/* GPP_C10:	UART0_RTS#		*/
+	PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+	/* GPP_C11:	UART0_CTS#		*/
+	PAD_CFG_NF(GPP_C11, UP_20K, DEEP, NF1),
+	/* GPP_C12:	Not Connected		*/
+	PAD_NC(GPP_C12, UP_20K),
+	/* GPP_C13:	Not Connected		*/
+	PAD_NC(GPP_C13, UP_20K),
+	/* GPP_C14:	Not Connected		*/
+	PAD_NC(GPP_C14, UP_20K),
+	/* GPP_C15:	Not Connected		*/
+	PAD_NC(GPP_C15, UP_20K),
+	/* GPP_C16:	DAT_I2C_TP		*/
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* GPP_C17:	CLK_I2C_TP		*/
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* GPP_C18:	TOUCH_I2C_SDA		*/
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* GPP_C19:	TOUCH_I2C_CLK		*/
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* GPP_C22:	Not Connected		*/
+	PAD_NC(GPP_C22, NONE),
+	/* GPP_C23:	TOUCHPAD_INT		*/
+	PAD_CFG_GPI_APIC_LOW(GPP_C23, NONE, PLTRST),
+	/* GPP_D0:	Not Connected		*/
+	PAD_NC(GPP_D0, DN_20K),
+	/* GPP_D1:	Not Connected		*/
+	PAD_NC(GPP_D1, DN_20K),
+	/* GPP_D2:	Not Connected		*/
+	PAD_NC(GPP_D2, DN_20K),
+	/* GPP_D3:	Not Connected		*/
+	PAD_NC(GPP_D3, DN_20K),
+	/* GPP_D4:	Not Connected		*/
+	PAD_NC(GPP_D4, DN_20K),
+	/* GPP_D5:	Not Connected		*/
+	PAD_NC(GPP_D5, DN_20K),
+	/* GPP_D6:	Not Connected		*/
+	PAD_NC(GPP_D6, DN_20K),
+	/* GPP_D7:	Not Connected		*/
+	PAD_NC(GPP_D7, DN_20K),
+	/* GPP_D8:	Not Connected		*/
+	PAD_NC(GPP_D8, DN_20K),
+	/* GPP_D9:	VOLUME_UP		*/
+	PAD_NC(GPP_D9, DN_20K),
+	/* GPP_D10:	VOLUME_DOWN		*/
+	PAD_NC(GPP_D10, DN_20K),
+	/* GPP_D11:	Not Connected		*/
+	PAD_NC(GPP_D11, DN_20K),
+	/* GPP_D12:	Not Connected		*/
+	PAD_NC(GPP_D12, DN_20K),
+	/* GPP_D13:	Not Connected		*/
+	PAD_NC(GPP_D13, DN_20K),
+	/* GPP_D14:	GPP_D14			*/
+	PAD_NC(GPP_D14, DN_20K),
+	/* GPP_D15:	GPP_D15			*/
+	PAD_NC(GPP_D15, DN_20K),
+	/* GPP_D16:	GPP_D16			*/
+	PAD_NC(GPP_D16, DN_20K),
+	/* GPP_D17:	PCH_AUDIO_PWREN		*/
+	PAD_NC(GPP_D17, DN_20K),
+	/* GPP_D18:	Not Connected		*/
+	PAD_NC(GPP_D18, DN_20K),
+	/* GPP_D19:	Not Connected		*/
+	PAD_NC(GPP_D19, DN_20K),
+	/* GPP_D20:	WIFI_OFF_N_MCP		*/
+	PAD_CFG_TERM_GPO(GPP_D20, 1, UP_20K, DEEP),
+	/* GPP_D21:	Not Connected		*/
+	PAD_NC(GPP_D21, DN_20K),
+	/* GPP_D22:	Not Connected		*/
+	PAD_NC(GPP_D22, DN_20K),
+	/* GPP_D23:	Not Connected		*/
+	PAD_NC(GPP_D23, DN_20K),
+	/* GPP_E0:	Not Connected		*/
+	PAD_NC(GPP_E0, DN_20K),
+	/* GPP_E1:	Not Connected		*/
+	PAD_NC(GPP_E1, DN_20K),
+	/* GPP_E2:	SATA2_SSD_Type		*/
+	PAD_NC(GPP_E2, DN_20K),
+	/* GPP_E3:	Not Connected		*/
+	PAD_NC(GPP_E3, DN_20K),
+	/* GPP_E4:	Not Connected		*/
+	PAD_NC(GPP_E4, DN_20K),
+	/* GPP_E5:	Not Connected		*/
+	PAD_NC(GPP_E5, DN_20K),
+	/* GPP_E6:	SATA2_SSD_DEVSLP	*/
+	PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1),
+	/* GPP_E7:	TOUCH_PANEL_INT_N	*/
+	PAD_NC(GPP_E7, DN_20K),
+	/* GPP_E8:	Not Connected		*/
+	PAD_NC(GPP_E8, DN_20K),
+	/* GPP_E9:	USB2_P1_WP1_OC_N	*/
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* GPP_E10:	USB2_P2_WP2_OC_N	*/
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	/* GPP_E11:	USB2_P3_WP2_OC_N	*/
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	/* GPP_E12:	Not Connected		*/
+	PAD_NC(GPP_E12, DN_20K),
+	/* GPP_E13:	DDI1_HPD		*/
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* GPP_E14:	DDI2_HPD		*/
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15:  SMC_SMI_N                      */
+	PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE),
+	/* E16:  SMC_SCI_N                      */
+	PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL),
+	/* GPP_E17:	EDP_HPD			*/
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+	/* GPP_E18:	DDI1_DDC_SCL		*/
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+	/* GPP_E19:	DDI1_DDC_SDA		*/
+	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
+	/* GPP_E20:	Not Connected		*/
+	PAD_NC(GPP_E20, DN_20K),
+	/* GPP_E21:	DDI2_DDC_SDA		*/
+	PAD_NC(GPP_E21, DN_20K),
+	/* GPP_E22:	Not Connected		*/
+	PAD_NC(GPP_E22, DN_20K),
+	/* GPP_E23:	TOUCH_PANEL_RESET_N	*/
+	PAD_NC(GPP_E23, DN_20K),
+	/* GPP_F0:	Not Connected		*/
+	PAD_NC(GPP_F0, DN_20K),
+	/* GPP_F1:	Not Connected		*/
+	PAD_NC(GPP_F1, DN_20K),
+	/* GPP_F2:	Not Connected		*/
+	PAD_NC(GPP_F2, DN_20K),
+	/* GPP_F3:	Not Connected		*/
+	PAD_NC(GPP_F3, DN_20K),
+	/* GPP_F4:	GSENSOR_I2C_SDA		*/
+	PAD_NC(GPP_F4, DN_20K),
+	/* GPP_F5:	GSENSOR_I2C_SCL		*/
+	PAD_NC(GPP_F5, DN_20K),
+	/* GPP_F6:	Not Connected		*/
+	PAD_NC(GPP_F6, DN_20K),
+	/* GPP_F7:	Not Connected		*/
+	PAD_NC(GPP_F7, DN_20K),
+	/* GPP_F8:	Not Connected		*/
+	PAD_NC(GPP_F8, NONE),
+	/* GPP_F9:	Not Connected		*/
+	PAD_NC(GPP_F9, NONE),
+	/* GPP_F10:	ACCEL2_INT		*/
+	PAD_NC(GPP_F10, DN_20K),
+	/* GPP_F11:	ACCEL1_INT		*/
+	PAD_NC(GPP_F11, DN_20K),
+	/* GPP_F12:	Not Connected		*/
+	PAD_NC(GPP_F12, DN_20K),
+	/* GPP_F13:	Not Connected		*/
+	PAD_NC(GPP_F13, DN_20K),
+	/* GPP_F14:	Not Connected		*/
+	PAD_NC(GPP_F14, DN_20K),
+	/* GPP_F15:	Not Connected		*/
+	PAD_NC(GPP_F15, DN_20K),
+	/* GPP_F16:	Not Connected		*/
+	PAD_NC(GPP_F16, DN_20K),
+	/* GPP_F17:	Not Connected		*/
+	PAD_NC(GPP_F17, DN_20K),
+	/* GPP_F18:	Not Connected		*/
+	PAD_NC(GPP_F18, DN_20K),
+	/* GPP_F19:	Not Connected		*/
+	PAD_NC(GPP_F19, DN_20K),
+	/* GPP_F20:	Not Connected		*/
+	PAD_NC(GPP_F20, DN_20K),
+	/* GPP_F21:	Not Connected		*/
+	PAD_NC(GPP_F21, DN_20K),
+	/* GPP_F22:	Not Connected		*/
+	PAD_NC(GPP_F22, DN_20K),
+	/* GPP_F23:	Not Connected		*/
+	PAD_NC(GPP_F23, DN_20K),
+	/* GPP_G0:	Not Connected		*/
+	PAD_NC(GPP_G0, NONE),
+	/* GPP_G1:	Not Connected		*/
+	PAD_NC(GPP_G1, NONE),
+	/* GPP_G2:	Not Connected		*/
+	PAD_NC(GPP_G2, NONE),
+	/* GPP_G3:	Not Connected		*/
+	PAD_NC(GPP_G3, NONE),
+	/* GPP_G4:	Not Connected		*/
+	PAD_NC(GPP_G4, NONE),
+	/* GPP_G5:	Not Connected		*/
+	PAD_NC(GPP_G5, NONE),
+	/* GPP_G6:	Not Connected		*/
+	PAD_NC(GPP_G6, NONE),
+	/* GPP_G7:	Not Connected		*/
+	PAD_NC(GPP_G7, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c b/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c
new file mode 100644
index 0000000000..f09f37b094
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */
+	0x10ec111e, /* Subsystem ID */
+	36,	    /* Number of jacks (NID entries) */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID Verb-table */
+	AZALIA_SUBVENDOR(0, 0x10ec111e),
+
+	/* Pin Widget Verb-table */
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a61120),
+	AZALIA_PIN_CFG(0, 0x14, 0x90171110),
+	AZALIA_PIN_CFG(0, 0x15, 0x042B1010),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x18, 0x04AB1020),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1A, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1B, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1D, 0x411111F0),
+	AZALIA_PIN_CFG(0, 0x1E, 0x411111F0),
+
+	/* Reset to D0 */
+	0x00170500,
+	0x00170500,
+	0x00170500,
+	0x00170500,
+
+	/* Reset Register */
+	0x0205001A,
+	0x02048003,
+	0x0205001A,
+	0x0204C003,
+
+	/* Widget node 0x20 */
+	0x02050018,
+	0x02040184, /* Stock: 0x02043984 */
+	0x0205001C,
+	0x02040800,
+
+	/* ALC269 Default 1 */
+	0x02050024,
+	0x02040000,
+	0x02050004,
+	0x02040080,
+
+	/* ALC269 Default 2 */
+	0x02050008,
+	0x02040300,
+	0x0205000C,
+	0x02043F00,
+
+	/* ALC269 Default 4 */
+	0x02050015,
+	0x02048002,
+	0x02050015,
+	0x02048002,
+
+	/* ALC269 Default 4 */
+	0x00C37080,
+	0x00270610,
+	0x00D37080,
+	0x00370610,
+
+	/*
+	 * Equalizer:
+	 *
+	 * AGC
+	 * Threshold:	- 6.00 dB
+	 * Front Boost:	+ 6.00 dB
+	 * Post Boost:	+ 6.00 dB
+	 *
+	 * Low Pass Filter
+	 * Boost Gain:	Enabled
+	 * BW:		200Hz
+	 * Gain:	+ 4.00 dB
+	 *
+	 * Band Pass Filter 1
+	 * Fc:		240Hz
+	 * BW:		400Hz
+	 * Gain:	- 4.00 dB
+	 *
+	 * Band Pass Filter 2
+	 * Fc:		16000Hz
+	 * BW:		1000Hz
+	 * Gain:	+ 12.00 dB
+	 *
+	 * High Pass Filter
+	 * Boost Gain:	Enabled
+	 * BW:		200Hz
+	 * Gain:	- 4.00 dB
+	 *
+	 * Class D Amp
+	 * Power:	2.5W
+	 * Resistance:	4ohms
+	 *
+	 * EQ Output
+	 * Left:	+ 0.00 dB
+	 * Right:	+ 0.00 dB
+	 *
+	 * VARQ
+	 * Q:		0.707
+	 */
+
+	0x05350000,
+	0x053404DA,
+	0x0535001d,
+	0x05340800,
+
+	0x0535001e,
+	0x05340800,
+	0x05350003,
+	0x05341F7A,
+
+	0x05350004,
+	0x0534FA18,
+	0x0535000F,
+	0x0534C295,
+
+	0x05350010,
+	0x05341D73,
+	0x05350011,
+	0x0534FA18,
+
+	0x05350012,
+	0x05341E08,
+	0x05350013,
+	0x05341C10,
+
+	0x05350014,
+	0x05342FB2,
+	0x0535001B,
+	0x05341F2C,
+
+	0x0535001C,
+	0x0534095C,
+	0x05450000,
+	0x05440000,
+
+	0x0545001d,
+	0x05440800,
+	0x0545001e,
+	0x05440800,
+
+	0x05450003,
+	0x05441F7A,
+	0x05450004,
+	0x0544FA18,
+
+	0x0545000F,
+	0x0544C295,
+	0x05450010,
+	0x05441D73,
+
+	0x05450011,
+	0x0544FA18,
+	0x05450012,
+	0x05441E08,
+
+	0x05450013,
+	0x05441C10,
+	0x05450014,
+	0x05442FB2,
+
+	0x0545001B,
+	0x05441F2C,
+	0x0545001C,
+	0x0544095C,
+
+	0x05350000,
+	0x0534C4DA,
+	0x02050038,
+	0x02044901,
+
+	0x02050013,
+	0x0204422F,
+	0x02050016,
+	0x02044E50,
+
+	0x02050012,
+	0x0204EBC4,
+	0x02050020,
+	0x020451FF,
+
+	0x8086280b, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+	4,	    /* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x07, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/starlabs/labtop/variants/kbl/romstage.c b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c
new file mode 100644
index 0000000000..098f753f1d
--- /dev/null
+++ b/src/mainboard/starlabs/labtop/variants/kbl/romstage.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <option.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+#include <types.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	const u16 rcomp_resistor[] = {121, 81, 100};
+	const u16 rcomp_target[] = {100, 40, 20, 20, 26};
+
+	memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor));
+	memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target));
+
+	mem_cfg->MemorySpdPtr00 = spd_cbfs_map(6);
+	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+	mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
+
+	const uint8_t ht = get_uint_option("hyper_threading",
+		mupd->FspmConfig.HyperThreading);
+	mupd->FspmConfig.HyperThreading = ht;
+}